32 float IN 0 abs.spindle.in <== spindle-fb-rps 32 bit OUT FALSE abs.spindle.is-negative 32 bit OUT FALSE abs.spindle.is-positive 32 float OUT 0 abs.spindle.out ==> spindle-fb-rps-abs 32 bit OUT FALSE abs.spindle.sign 32 s32 OUT 50 abs.spindle.time 10 bit OUT FALSE halui.spindle.0.brake-is-on 10 bit IN FALSE halui.spindle.0.brake-off 10 bit IN FALSE halui.spindle.0.brake-on 10 bit IN FALSE halui.spindle.0.decrease 10 bit IN FALSE halui.spindle.0.forward <== spindle-manual-cw 10 bit IN FALSE halui.spindle.0.increase 10 bit OUT TRUE halui.spindle.0.is-on 10 bit IN TRUE halui.spindle.0.override.count-enable 10 s32 IN 0 halui.spindle.0.override.counts <== spindleoverride-incr 10 bit IN FALSE halui.spindle.0.override.decrease 10 bit IN TRUE halui.spindle.0.override.direct-value 10 bit IN FALSE halui.spindle.0.override.increase 10 float IN 0.01 halui.spindle.0.override.scale 10 float OUT 1 halui.spindle.0.override.value 10 bit IN FALSE halui.spindle.0.reverse <== spindle-manual-ccw 10 bit OUT FALSE halui.spindle.0.runs-backward 10 bit OUT TRUE halui.spindle.0.runs-forward 10 bit IN FALSE halui.spindle.0.start 10 bit IN FALSE halui.spindle.0.stop <== spindle-manual-stop 26 bit IN FALSE hm2_5i25.0.7i76.0.3.output-11 <== spindle-brake 26 bit IN FALSE hm2_5i25.0.7i76.0.3.spindir <== spindle-ccw 26 bit IN TRUE hm2_5i25.0.7i76.0.3.spinena <== spindle-enable 26 float IN 0.396 hm2_5i25.0.7i76.0.3.spinout <== spindle-output 26 bit I/O FALSE hm2_5i25.0.encoder.03.index-enable <=> spindle-index-enable 26 float OUT 58.85547 hm2_5i25.0.encoder.03.position ==> spindle-revs 26 float OUT 0.5878586 hm2_5i25.0.encoder.03.velocity ==> spindle-vel-fb-rps 35 float IN 0 lowpass.spindle.in <== spindle-fb-rps-abs 35 bit IN FALSE lowpass.spindle.load 35 float OUT 0 lowpass.spindle.out ==> spindle-fb-rps-abs-filtered 35 s32 OUT 150 lowpass.spindle.time 47 float IN 0.396 mux2.spindleCcw.in0 <== spindleCcwScaleCcw 47 float IN 11.604 mux2.spindleCcw.in1 <== spindleCcwScaleCw 47 float OUT 0.396 mux2.spindleCcw.out ==> spindle-output 47 bit IN FALSE mux2.spindleCcw.sel <== spindle-ccw 47 s32 OUT 222 mux2.spindleCcw.time 68 bit IN TRUE pyvcp.spindle-at-speed-led <== spindle-at-speed 68 float IN 0 pyvcp.spindle-speed <== spindle-fb-rpm-abs-filtered 38 float IN -0.004 scale.spindleCcw.gain 38 float IN 2901 scale.spindleCcw.in <== spindleSpeed 38 float IN 12 scale.spindleCcw.offset 38 float OUT 0.396 scale.spindleCcw.out ==> spindleCcwScaleCcw 38 s32 OUT 296 scale.spindleCcw.time 38 float IN 0.004 scale.spindleCw.gain 38 float IN 2901 scale.spindleCw.in <== spindleSpeed 38 float IN 0 scale.spindleCw.offset 38 float OUT 11.604 scale.spindleCw.out ==> spindleCcwScaleCw 38 s32 OUT 356 scale.spindleCw.time 44 s32 OUT 0 soincr.out-s ==> spindleoverride-incr 19 bit IN FALSE spindle.0.amp-fault-in 19 bit IN TRUE spindle.0.at-speed <== spindle-at-speed 19 bit OUT FALSE spindle.0.brake ==> spindle-brake 19 bit OUT TRUE spindle.0.forward ==> spindle-cw 19 bit I/O FALSE spindle.0.index-enable <=> spindle-index-enable 19 bit IN FALSE spindle.0.inhibit 19 bit IN FALSE spindle.0.is-oriented 19 bit OUT FALSE spindle.0.locked 19 bit OUT TRUE spindle.0.on ==> spindle-enable 19 bit OUT FALSE spindle.0.orient 19 float OUT 0 spindle.0.orient-angle 19 s32 IN 0 spindle.0.orient-fault 19 s32 OUT 0 spindle.0.orient-mode 19 bit OUT FALSE spindle.0.reverse ==> spindle-ccw 19 float IN 58.85547 spindle.0.revs <== spindle-revs 19 float OUT 48.35 spindle.0.speed-cmd-rps 19 float IN 0.5878586 spindle.0.speed-in <== spindle-vel-fb-rps 19 float OUT 2901 spindle.0.speed-out ==> spindle-vel-cmd-rpm 19 float OUT 2901 spindle.0.speed-out-abs ==> spindleSpeed 19 float OUT 48.35 spindle.0.speed-out-rps ==> spindle-vel-cmd-rps 19 float OUT 48.35 spindle.0.speed-out-rps-abs ==> spindle-vel-cmd-rps-abs bit TRUE spindle-at-speed ==> pyvcp.spindle-at-speed-led ==> spindle.0.at-speed bit FALSE spindle-brake <== spindle.0.brake bit FALSE spindle-ccw ==> mux2.spindleCcw.sel <== spindle.0.reverse bit TRUE spindle-cw <== spindle.0.forward bit TRUE spindle-enable <== spindle.0.on float 0 spindle-fb-rpm-abs-filtered ==> pyvcp.spindle-speed float 0 spindle-fb-rps ==> abs.spindle.in float 0 spindle-fb-rps-abs <== abs.spindle.out ==> lowpass.spindle.in float 0 spindle-fb-rps-abs-filtered <== lowpass.spindle.out bit FALSE spindle-index-enable <=> spindle.0.index-enable bit FALSE spindle-manual-ccw ==> halui.spindle.0.reverse bit FALSE spindle-manual-cw ==> halui.spindle.0.forward bit FALSE spindle-manual-stop ==> halui.spindle.0.stop float 0.396 spindle-output <== mux2.spindleCcw.out float 58.85596 spindle-revs ==> spindle.0.revs float 2901 spindle-vel-cmd-rpm <== spindle.0.speed-out float 48.35 spindle-vel-cmd-rps <== spindle.0.speed-out-rps float 48.35 spindle-vel-cmd-rps-abs <== spindle.0.speed-out-rps-abs float 0.5871588 spindle-vel-fb-rps ==> spindle.0.speed-in float 0.396 spindleCcwScaleCcw ==> mux2.spindleCcw.in0 <== scale.spindleCcw.out float 11.604 spindleCcwScaleCw ==> mux2.spindleCcw.in1 <== scale.spindleCw.out float 2901 spindleSpeed ==> scale.spindleCcw.in ==> scale.spindleCw.in <== spindle.0.speed-out-abs s32 0 spindleoverride-incr ==> halui.spindle.0.override.counts 32 s32 RW 8908 abs.spindle.tmax 32 bit RO FALSE abs.spindle.tmax-increased 35 float RW 1 lowpass.spindle.gain 35 s32 RW 2272 lowpass.spindle.tmax 35 bit RO FALSE lowpass.spindle.tmax-increased 47 s32 RW 1928 mux2.spindleCcw.tmax 47 bit RO FALSE mux2.spindleCcw.tmax-increased 38 s32 RW 2188 scale.spindleCcw.tmax 38 bit RO FALSE scale.spindleCcw.tmax-increased 38 s32 RW 7208 scale.spindleCw.tmax 38 bit RO FALSE scale.spindleCw.tmax-increased 00032 7f2ac1e14185 7f2ac21dd250 YES 1 abs.spindle 00035 7f2ac1e0f195 7f2ac21dd2a0 YES 1 lowpass.spindle 00047 7f2ac1dd0185 7f2ac21dd930 YES 1 mux2.spindleCcw 00038 7f2ac1e0a175 7f2ac21dd320 YES 1 scale.spindleCcw 00038 7f2ac1e0a175 7f2ac21dd2f0 YES 1 scale.spindleCw 12 mux2.spindleCcw 13 scale.spindleCw 14 scale.spindleCcw 15 abs.spindle 16 lowpass.spindle