ilya@Debian9:/opt/litehm2$ su Password: root@Debian9:/opt/litehm2# make make -f Makefile.target TARGET=board make[1]: Entering directory '/opt/litehm2' dd if=/dev/zero of=build/board/firmware/firmware.bin bs=32k count=1 1+0 records in 1+0 records out 32768 bytes (33 kB, 32 KiB) copied, 6.9206e-05 s, 473 MB/s dd if=/dev/zero of=build/board/firmware/loader.bin bs=4k count=1 1+0 records in 1+0 records out 4096 bytes (4.1 kB, 4.0 KiB) copied, 6.3192e-05 s, 64.8 MB/s ./litehm2.py --builddir=build/board --config=configs/board.conf INFO:SoC: __ _ __ _ __ INFO:SoC: / / (_) /____ | |/_/ INFO:SoC: / /__/ / __/ -_)> < INFO:SoC: /____/_/\__/\__/_/|_| INFO:SoC: Build your hardware, easily! INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Creating SoC... (2024-03-14 06:00:05) INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:FPGA device : xc6slx16-2-ftg256. INFO:SoC:System clock: 80.000MHz. INFO:SoCBusHandler:Creating Bus Handler... INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoCBusHandler:Adding reserved Bus Regions... INFO:SoCBusHandler:Bus Handler created. INFO:SoCCSRHandler:Creating CSR Handler... INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoCCSRHandler:Adding reserved CSRs... INFO:SoCCSRHandler:CSR Handler created. INFO:SoCIRQHandler:Creating IRQ Handler... INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations). INFO:SoCIRQHandler:Adding reserved IRQs... INFO:SoCIRQHandler:IRQ Handler created. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Initial SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoC:IRQ Handler (up to 32 Locations). INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Controller ctrl added. INFO:SoC:CPU vexriscv added. INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000). INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False. INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000. INFO:SoC:CPU vexriscv setting reset address to 0x00000000. INFO:SoC:CPU vexriscv adding Bus Master(s). INFO:SoCBusHandler:cpu_bus0 added as Bus Master. INFO:SoCBusHandler:cpu_bus1 added as Bus Master. INFO:SoC:CPU vexriscv adding Interrupt(s). INFO:SoC:CPU vexriscv adding SoC components. INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00001000, Mode: RX, Cached: True Linker: False. INFO:SoCBusHandler:rom added as Bus Slave. INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00001000, Mode: RX, Cached: True Linker: False. INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False. INFO:SoCBusHandler:sram added as Bus Slave. INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False. INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RWX, Cached: True Linker: False. INFO:SoCBusHandler:main_ram added as Bus Slave. INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RWX, Cached: True Linker: False. INFO:SoCIRQHandler:uart IRQ allocated at Location 0. INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1. INFO:SoCRegion:Region size rounded internally from 0x00005000 to 0x00008000. INFO:SoCBusHandler:Allocating IO Region of size 0x00005000... INFO:SoCRegion:Region size rounded internally from 0x00005000 to 0x00008000. INFO:SoCBusHandler:ethmac Region allocated at Origin: 0x80000000, Size: 0x00005000, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:ethmac added as Bus Slave. INFO:SoCIRQHandler:ethmac IRQ allocated at Location 2. INFO:SoCBusHandler:Allocating Cached Region of size 0x00400000... INFO:SoCRegion:Region size rounded internally from 0xffffffff to 0x100000000. INFO:SoCBusHandler:spiflash Region allocated at Origin: 0x00400000, Size: 0x00400000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:spiflash added as Bus Slave. INFO:SoCBusHandler:hostmot2 Region added at Origin: 0x70000000, Size: 0x00010000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:hostmot2 added as Bus Slave. INFO:SoC:CSR Bridge csr added. INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:csr added as Bus Slave. INFO:SoCCSRHandler:csr added as CSR Master. INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 7). INFO:SoCCSRHandler:ctrl CSR allocated at Location 0. INFO:SoCCSRHandler:ethmac CSR allocated at Location 1. INFO:SoCCSRHandler:ethphy CSR allocated at Location 2. INFO:SoCCSRHandler:hostmot2 CSR allocated at Location 3. INFO:SoCCSRHandler:leds CSR allocated at Location 4. INFO:SoCCSRHandler:spiflash_core CSR allocated at Location 5. INFO:SoCCSRHandler:spiflash_phy CSR allocated at Location 6. INFO:SoCCSRHandler:timer0 CSR allocated at Location 7. INFO:SoCCSRHandler:uart CSR allocated at Location 8. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Finalized SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. IO Regions: (1) io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False Bus Regions: (7) rom : Origin: 0x00000000, Size: 0x00001000, Mode: RX, Cached: True Linker: False spiflash : Origin: 0x00400000, Size: 0x00400000, Mode: RW, Cached: True Linker: False sram : Origin: 0x10000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False main_ram : Origin: 0x40000000, Size: 0x00004000, Mode: RWX, Cached: True Linker: False hostmot2 : Origin: 0x70000000, Size: 0x00010000, Mode: RW, Cached: True Linker: False ethmac : Origin: 0x80000000, Size: 0x00005000, Mode: RW, Cached: False Linker: False csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False Bus Masters: (2) - cpu_bus0 - cpu_bus1 Bus Slaves: (7) - rom - sram - main_ram - ethmac - spiflash - hostmot2 - csr INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). CSR Locations: (9) - ctrl : 0 - ethmac : 1 - ethphy : 2 - hostmot2 : 3 - leds : 4 - spiflash_core : 5 - spiflash_phy : 6 - timer0 : 7 - uart : 8 INFO:SoC:IRQ Handler (up to 32 Locations). IRQ Locations: (3) - uart : 0 - timer0 : 1 - ethmac : 2 INFO:SoC:-------------------------------------------------------------------------------- INFO:S6PLL:Config: divclk_divide : 1 clkout1_freq : 200.00MHz clkout1_divide: 4 clkout1_phase : 0.00° clkout0_freq : 80.00MHz clkout0_divide: 10 clkout0_phase : 0.00° vco : 800.00MHz clkfbout_mult : 32 INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:SoC Hierarchy: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC: LiteHM2 └─── crg (_CRG) │ └─── pll (S6PLL) │ │ └─── [BUFG] │ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [PLL_ADV] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] └─── bus (SoCBusHandler) │ └─── _interconnect (InterconnectShared) │ │ └─── arbiter (Arbiter) │ │ │ └─── rr (RoundRobin) │ │ └─── decoder (Decoder) │ │ └─── timeout (Timeout) │ │ │ └─── waittimer_0* (WaitTimer) └─── csr (SoCCSRHandler) └─── irq (SoCIRQHandler) └─── ctrl (SoCController) │ └─── _reset (CSRStorage) │ └─── _scratch (CSRStorage) │ └─── _bus_errors (CSRStatus) └─── cpu (VexRiscv) │ └─── [VexRiscv] └─── rom (SRAM) └─── sram (SRAM) └─── main_ram (SRAM) └─── uart (UART) │ └─── ev (EventManager) │ │ └─── eventsourceprocess_0* (EventSourceProcess) │ │ └─── eventsourceprocess_1* (EventSourceProcess) │ └─── tx_fifo (SyncFIFO) │ └─── rx_fifo (SyncFIFO) └─── timer0 (Timer) │ └─── ev (EventManager) │ │ └─── eventsourceprocess_0* (EventSourceProcess) └─── leds (LedChaser) │ └─── waittimer_0* (WaitTimer) └─── ethphy (LiteEthPHYRGMII) │ └─── crg (LiteEthPHYRGMIICRG) │ │ └─── _reset (CSRStorage) │ │ └─── hw_reset (LiteEthPHYHWReset) │ │ └─── [ODDR2] │ │ └─── [BUFG] │ │ └─── [IODELAY2] │ └─── tx (LiteEthPHYRGMIITX) │ │ └─── [IODELAY2] │ │ └─── [ODDR2] │ │ └─── [IODELAY2] │ │ └─── [IODELAY2] │ │ └─── [ODDR2] │ │ └─── [IODELAY2] │ │ └─── [ODDR2] │ │ └─── [IODELAY2] │ │ └─── [ODDR2] │ │ └─── [ODDR2] │ └─── rx (LiteEthPHYRGMIIRX) │ │ └─── [IODELAY2] │ │ └─── [IBUF] │ │ └─── [IBUF] │ │ └─── [IDDR2] │ │ └─── [IODELAY2] │ │ └─── [IODELAY2] │ │ └─── [IODELAY2] │ │ └─── [IDDR2] │ │ └─── [IODELAY2] │ │ └─── [IBUF] │ │ └─── [IBUF] │ │ └─── [IDDR2] │ │ └─── [IBUF] │ │ └─── [IDDR2] │ │ └─── [IDDR2] └─── ethmac (LiteEthMAC) │ └─── core (LiteEthMACCore) │ │ └─── tx_datapath (TXDatapath) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) │ │ │ │ └─── liteethmaccrc32_0* (LiteEthMACCRC32) │ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_1* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_2* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_3* (LiteEthMACCRCEngine) │ │ │ │ └─── fsm_0* (FSM) │ │ │ │ └─── buffer_0* (Buffer) │ │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ │ └─── pipeline (Pipeline) │ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) │ │ │ │ └─── asyncfifo_0* (AsyncFIFO) │ │ │ │ │ └─── fifo (AsyncFIFO) │ │ │ │ │ │ └─── graycounter_0* (GrayCounter) │ │ │ │ │ │ └─── graycounter_1* (GrayCounter) │ │ │ └─── strideconverter_0* (StrideConverter) │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacgap_0* (LiteEthMACGap) │ │ │ │ └─── fsm (FSM) │ │ │ └─── pipeline_0* (Pipeline) │ │ └─── rx_datapath (RXDatapath) │ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) │ │ │ └─── strideconverter_0* (StrideConverter) │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _upconverter_0* (_UpConverter) │ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) │ │ │ │ └─── asyncfifo_0* (AsyncFIFO) │ │ │ │ │ └─── fifo (AsyncFIFO) │ │ │ │ │ │ └─── graycounter_0* (GrayCounter) │ │ │ │ │ │ └─── graycounter_1* (GrayCounter) │ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) │ │ │ │ └─── fsm (FSM) │ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) │ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) │ │ │ │ └─── liteethmaccrc32_0* (LiteEthMACCRC32) │ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_1* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_2* (LiteEthMACCRCEngine) │ │ │ │ │ └─── liteethmaccrcengine_3* (LiteEthMACCRCEngine) │ │ │ │ └─── syncfifo_0* (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm_0* (FSM) │ │ │ │ └─── buffer_0* (Buffer) │ │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ │ └─── pipeline (Pipeline) │ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) │ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) │ │ │ └─── pipeline_0* (Pipeline) │ └─── interface (LiteEthMACWishboneInterface) │ │ └─── sram (LiteEthMACSRAM) │ │ │ └─── writer (LiteEthMACSRAMWriter) │ │ │ │ └─── ev (EventManager) │ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) │ │ │ │ └─── stat_fifo (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm (FSM) │ │ │ └─── reader (LiteEthMACSRAMReader) │ │ │ │ └─── ev (EventManager) │ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) │ │ │ │ └─── syncfifo_0* (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── syncfifo_1* (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm (FSM) │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) │ │ └─── sram_4* (SRAM) │ │ └─── sram_5* (SRAM) │ │ └─── sram_6* (SRAM) │ │ └─── sram_7* (SRAM) │ │ └─── sram_8* (SRAM) │ │ └─── sram_9* (SRAM) │ │ └─── decoder_0* (Decoder) └─── spiflash_phy (LiteSPIPHY) │ └─── spiflash_phy (LiteSPISDRPHYCore) │ │ └─── resyncreg_0* (ResyncReg) │ │ └─── clkgen (LiteSPIClkGen) │ │ └─── waittimer_0* (WaitTimer) │ │ └─── fsm (FSM) └─── spiflash_core (LiteSPI) │ └─── crossbar (LiteSPICrossbar) │ │ └─── rr (RoundRobin) │ │ └─── tx_mux (Multiplexer) │ │ └─── rx_demux (Demultiplexer) │ └─── mmap (LiteSPIMMAP) │ │ └─── waittimer_0* (WaitTimer) │ │ └─── fsm (FSM) │ └─── master (LiteSPIMaster) │ │ └─── syncfifo_0* (SyncFIFO) │ │ │ └─── buffer_0* (Buffer) │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ └─── pipeline (Pipeline) │ │ └─── syncfifo_1* (SyncFIFO) │ │ │ └─── buffer_0* (Buffer) │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ └─── pipeline (Pipeline) └─── hostmot2 (HostMot2) │ └─── [TopHostMot2] └─── csr_bridge (Wishbone2CSR) │ └─── fsm_0* (FSM) └─── csr_bankarray (CSRBankArray) │ └─── csrbank_0* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstatus_0* (CSRStatus) │ └─── csrbank_1* (CSRBank) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstatus_1* (CSRStatus) │ │ └─── csrstatus_2* (CSRStatus) │ │ └─── csrstatus_3* (CSRStatus) │ │ └─── csrstatus_4* (CSRStatus) │ │ └─── csrstatus_5* (CSRStatus) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstatus_6* (CSRStatus) │ │ └─── csrstatus_7* (CSRStatus) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstorage_2* (CSRStorage) │ │ └─── csrstatus_8* (CSRStatus) │ │ └─── csrstatus_9* (CSRStatus) │ │ └─── csrstatus_10* (CSRStatus) │ │ └─── csrstatus_11* (CSRStatus) │ │ └─── csrstorage_3* (CSRStorage) │ │ └─── csrstatus_12* (CSRStatus) │ │ └─── csrstatus_13* (CSRStatus) │ │ └─── csrstatus_14* (CSRStatus) │ └─── csrbank_2* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ └─── csrbank_3* (CSRBank) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstatus_1* (CSRStatus) │ └─── csrbank_4* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ └─── csrbank_5* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstorage_2* (CSRStorage) │ │ └─── csrstatus_0* (CSRStatus) │ └─── csrbank_6* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ └─── csrbank_7* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstorage_2* (CSRStorage) │ │ └─── csrstorage_3* (CSRStorage) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstatus_1* (CSRStatus) │ │ └─── csrstatus_2* (CSRStatus) │ │ └─── csrstorage_4* (CSRStorage) │ │ └─── csrstorage_5* (CSRStorage) │ │ └─── csrstatus_3* (CSRStatus) │ └─── csrbank_8* (CSRBank) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstatus_1* (CSRStatus) │ │ └─── csrstatus_2* (CSRStatus) │ │ └─── csrstatus_3* (CSRStatus) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstatus_4* (CSRStatus) │ │ └─── csrstatus_5* (CSRStatus) └─── csr_interconnect (InterconnectShared) * : Generated name. []: BlackBox. INFO:SoC:-------------------------------------------------------------------------------- Traceback (most recent call last): File "./litehm2.py", line 182, in main() File "./litehm2.py", line 179, in main builder.build(build_name="litehm2", run=False) File "/opt/litex/litex/litex/soc/integration/builder.py", line 335, in build self._generate_includes(with_bios=with_bios) File "/opt/litex/litex/litex/soc/integration/builder.py", line 183, in _generate_includes variables_contents = self._get_variables_contents() File "/opt/litex/litex/litex/soc/integration/builder.py", line 153, in _get_variables_contents for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software): File "/opt/litex/litex/litex/soc/integration/export.py", line 92, in get_cpu_mak selected_triple = select_triple(triple) File "/opt/litex/litex/litex/soc/integration/export.py", line 90, in select_triple raise OSError(msg) OSError: Unable to find any of the cross compilation toolchains: - riscv64-pc-linux-musl - riscv64-unknown-elf - riscv64-unknown-linux-gnu - riscv64-elf - riscv64-linux - riscv64-linux-gnu - riscv-sifive-elf - riscv64-none-elf - riscv32-unknown-elf - riscv32-unknown-linux-gnu - riscv32-elf - riscv-none-embed - riscv-none-elf Makefile.target:8: recipe for target 'litehm2' failed make[1]: *** [litehm2] Error 1 make[1]: Leaving directory '/opt/litehm2' Makefile:8: recipe for target 'bitstreams/board.bit' failed make: *** [bitstreams/board.bit] Error 2 root@Debian9:/opt/litehm2#