PnR Messages

Report Title PnR Report
Design File /home/cnc/Desktop/GOWIN/Projects/W5500/impl/gwsynthesis/W5500.vg
Physical Constraints File /home/cnc/Desktop/GOWIN/Projects/W5500/src/pins.cst
Timing Constraints File ---
Tool Version V1.9.10
Part Number GW1NR-LV9QN88C7/I6
Device GW1NR-9
Device Version C
Created Time Fri Aug 2 05:49:42 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.241s, Elapsed time = 0h 0m 0.248s Placement Phase 1: CPU time = 0h 0m 0.305s, Elapsed time = 0h 0m 0.308s Placement Phase 2: CPU time = 0h 0m 0.219s, Elapsed time = 0h 0m 0.217s Placement Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Total Placement: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.739s, Elapsed time = 0h 0m 0.735s Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 2s Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Time and Memory Usage CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 283MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 563/8640 7%
    --LUT,ALU,ROM16 563(539 LUT, 24 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 234/6693 4%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 231/6480 4%
    --I/O Register as Latch 0/213 0%
    --I/O Register as FF 3/213 2%
CLS 317/4320 8%
I/O Port 8 -
I/O Buf 8 -
    --Input Buf 3 -
    --Output Buf 5 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 0 0%
DSP 00%
PLL 0/2 0%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DHCEN 0/8 0%
DHCENC 0/4 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 1 7/25(28%)
bank 2 0/23(0%)
bank 3 1/23(4%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 1/8(13%)
LW 1/8(13%)
GCLK_PIN 1/3(34%)
PLL 0/2(0%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
sysclk_in_d PRIMARY TR TL BR BL
rst_n_d LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
sysclk_in 52/1 Y in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
rst_n 80/3 Y in IOT12[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
miso 74/1 Y in IOT38[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
sclk 75/1 Y out IOT38[A] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
mosi 73/1 Y out IOT39[A] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
sel 76/1 Y out IOT37[B] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
w5500_rst 77/1 Y out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
PINOUT_BLINK0_LED 48/1 Y out IOR24[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
88/3 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
87/3 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
86/3 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
85/3 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
84/3 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
83/3 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
82/3 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
81/3 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
80/3 rst_n in IOT12[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
79/3 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
77/1 w5500_rst out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
76/1 sel out IOT37[B] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
75/1 sclk out IOT38[A] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
74/1 miso in IOT38[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
73/1 mosi out IOT39[A] LVCMOS33 4 UP NA NA OFF NA OFF NA 3.3
72/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
71/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
70/1 - in IOT41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
69/1 - in IOT42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
68/1 - in IOT42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
17/2 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/2 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/2 - in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/2 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 - in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 - in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 - in IOB23[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOB23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/2 - in IOB29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
36/2 - in IOB29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
37/2 - in IOB31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/2 - in IOB31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/2 - in IOB33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/2 - in IOB33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/2 - in IOB41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/2 - in IOB41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/2 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/3 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
4/3 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
5/3 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
6/3 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
7/3 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
8/3 - out IOL13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.2
9/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
10/3 - in IOL14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
11/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
13/3 - in IOL22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
14/3 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
15/3 - in IOL26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
16/3 - in IOL26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
63/1 - in IOR5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/1 - in IOR12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/1 - in IOR12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/1 - in IOR13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
56/1 - in IOR14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
55/1 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
54/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
53/1 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
52/1 sysclk_in in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
51/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
50/1 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
49/1 - in IOR24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/1 PINOUT_BLINK0_LED out IOR24[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3