Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | /home/cnc/Desktop/GOWIN/Projects/W5500/src/SPI.v /home/cnc/Desktop/GOWIN/Projects/W5500/src/blink.v /home/cnc/Desktop/GOWIN/Projects/W5500/src/rio.v /home/cnc/Desktop/GOWIN/Projects/W5500/src/w5500.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10 |
Part Number | GW1NR-LV9QN88C7/I6 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Fri Aug 2 05:49:31 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | rio |
Synthesis Process | Running parser: CPU time = 0h 0m 0.518s, Elapsed time = 0h 0m 0.517s, Peak memory usage = 163.730MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.256s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 163.730MB Optimizing Phase 1: CPU time = 0h 0m 0.076s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 163.730MB Optimizing Phase 2: CPU time = 0h 0m 0.135s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 163.730MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 164.000MB Inferring Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 164.000MB Inferring Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 164.000MB Inferring Phase 3: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 164.000MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.135s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 164.000MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 164.000MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.026s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 164.000MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 193.480MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.112s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 193.480MB Generate output files: CPU time = 0h 0m 0.222s, Elapsed time = 0h 0m 0.245s, Peak memory usage = 193.480MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 193.480MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 8 |
I/O Buf | 8 |
    IBUF | 3 |
    OBUF | 5 |
Register | 234 |
    DFF | 12 |
    DFFE | 1 |
    DFFR | 20 |
    DFFP | 1 |
    DFFPE | 2 |
    DFFC | 84 |
    DFFCE | 114 |
LUT | 532 |
    LUT2 | 77 |
    LUT3 | 159 |
    LUT4 | 296 |
ALU | 23 |
    ALU | 23 |
INV | 8 |
    INV | 8 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 563(540 LUT, 23 ALU) / 8640 | 7% |
Register | 234 / 6693 | 4% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 234 / 6693 | 4% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
sysclk_in | Base | 20.000 | 50.0 | 0.000 | 10.000 | sysclk_in_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | sysclk_in | 50.000(MHz) | 82.121(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 7.823 |
Data Arrival Time | 12.419 |
Data Required Time | 20.242 |
From | w550013/tx_data_42_s1 |
To | w550013/SPI/mosi_s0 |
Launch Clk | sysclk_in[R] |
Latch Clk | sysclk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sysclk_in | |||
0.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | w550013/tx_data_42_s1/CLK |
0.878 | 0.340 | tC2Q | RF | 3 | w550013/tx_data_42_s1/Q |
1.589 | 0.711 | tNET | FF | 1 | w550013/SPI/n178_s200/I1 |
2.403 | 0.814 | tINS | FF | 1 | w550013/SPI/n178_s200/F |
3.115 | 0.711 | tNET | FF | 1 | w550013/SPI/n178_s193/I0 |
3.225 | 0.110 | tINS | FF | 1 | w550013/SPI/n178_s193/O |
3.936 | 0.711 | tNET | FF | 1 | w550013/SPI/n178_s189/I1 |
4.057 | 0.121 | tINS | FF | 1 | w550013/SPI/n178_s189/O |
4.769 | 0.711 | tNET | FF | 1 | w550013/SPI/n178_s185/I1 |
4.889 | 0.121 | tINS | FF | 2 | w550013/SPI/n178_s185/O |
5.601 | 0.711 | tNET | FF | 1 | w550013/SPI/n1197_s23/I2 |
6.210 | 0.609 | tINS | FF | 1 | w550013/SPI/n1197_s23/F |
6.921 | 0.711 | tNET | FF | 1 | w550013/SPI/n1197_s13/I2 |
7.530 | 0.609 | tINS | FF | 1 | w550013/SPI/n1197_s13/F |
8.242 | 0.711 | tNET | FF | 1 | w550013/SPI/n1197_s6/I3 |
8.706 | 0.464 | tINS | FF | 1 | w550013/SPI/n1197_s6/F |
9.417 | 0.711 | tNET | FF | 1 | w550013/SPI/n1197_s3/I0 |
10.182 | 0.765 | tINS | FF | 1 | w550013/SPI/n1197_s3/F |
10.893 | 0.711 | tNET | FF | 1 | w550013/SPI/n1197_s1/I1 |
11.707 | 0.814 | tINS | FF | 1 | w550013/SPI/n1197_s1/F |
12.419 | 0.711 | tNET | FF | 1 | w550013/SPI/mosi_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sysclk_in | |||
20.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
20.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | w550013/SPI/mosi_s0/CLK |
20.242 | -0.296 | tSu | 1 | w550013/SPI/mosi_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 4.427, 37.266%; route: 7.114, 59.875%; tC2Q: 0.340, 2.859% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:Slack | 9.598 |
Data Arrival Time | 10.644 |
Data Required Time | 20.242 |
From | w550013/SPI/cnt_4_s3 |
To | w550013/SPI/num_3_s0 |
Launch Clk | sysclk_in[R] |
Latch Clk | sysclk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sysclk_in | |||
0.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | w550013/SPI/cnt_4_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | w550013/SPI/cnt_4_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | w550013/SPI/sclk_r_s6/I1 |
2.403 | 0.814 | tINS | FF | 5 | w550013/SPI/sclk_r_s6/F |
3.115 | 0.711 | tNET | FF | 1 | w550013/SPI/n473_s6/I1 |
3.929 | 0.814 | tINS | FF | 3 | w550013/SPI/n473_s6/F |
4.640 | 0.711 | tNET | FF | 1 | w550013/SPI/n1230_s9/I1 |
5.455 | 0.814 | tINS | FF | 6 | w550013/SPI/n1230_s9/F |
6.166 | 0.711 | tNET | FF | 1 | w550013/SPI/n473_s3/I0 |
6.931 | 0.765 | tINS | FF | 1 | w550013/SPI/n473_s3/F |
7.642 | 0.711 | tNET | FF | 1 | w550013/SPI/n1232_s2/I1 |
8.457 | 0.814 | tINS | FF | 1 | w550013/SPI/n1232_s2/F |
9.168 | 0.711 | tNET | FF | 1 | w550013/SPI/n1232_s1/I0 |
9.933 | 0.765 | tINS | FF | 1 | w550013/SPI/n1232_s1/F |
10.644 | 0.711 | tNET | FF | 1 | w550013/SPI/num_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sysclk_in | |||
20.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
20.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | w550013/SPI/num_3_s0/CLK |
20.242 | -0.296 | tSu | 1 | w550013/SPI/num_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 4.787, 47.366%; route: 4.980, 49.273%; tC2Q: 0.340, 3.361% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:Slack | 9.704 |
Data Arrival Time | 10.538 |
Data Required Time | 20.242 |
From | w550013/Delay10_1_1_s0 |
To | w550013/Delay10_1_20_s0 |
Launch Clk | sysclk_in[R] |
Latch Clk | sysclk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sysclk_in | |||
0.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | w550013/Delay10_1_1_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | w550013/Delay10_1_1_s0/Q |
1.589 | 0.711 | tNET | FF | 1 | w550013/n247_s2/I1 |
2.403 | 0.814 | tINS | FF | 4 | w550013/n247_s2/F |
3.115 | 0.711 | tNET | FF | 1 | w550013/n244_s3/I1 |
3.929 | 0.814 | tINS | FF | 4 | w550013/n244_s3/F |
4.640 | 0.711 | tNET | FF | 1 | w550013/n241_s3/I1 |
5.455 | 0.814 | tINS | FF | 5 | w550013/n241_s3/F |
6.166 | 0.711 | tNET | FF | 1 | w550013/n236_s2/I2 |
6.775 | 0.609 | tINS | FF | 7 | w550013/n236_s2/F |
7.487 | 0.711 | tNET | FF | 1 | w550013/n232_s2/I1 |
8.301 | 0.814 | tINS | FF | 1 | w550013/n232_s2/F |
9.012 | 0.711 | tNET | FF | 1 | w550013/n231_s1/I1 |
9.827 | 0.814 | tINS | FF | 1 | w550013/n231_s1/F |
10.538 | 0.711 | tNET | FF | 1 | w550013/Delay10_1_20_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sysclk_in | |||
20.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
20.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | w550013/Delay10_1_20_s0/CLK |
20.242 | -0.296 | tSu | 1 | w550013/Delay10_1_20_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 4.681, 46.809%; route: 4.980, 49.795%; tC2Q: 0.340, 3.396% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:Slack | 9.753 |
Data Arrival Time | 10.488 |
Data Required Time | 20.242 |
From | w550013/SPI/cnt_4_s3 |
To | w550013/SPI/num_2_s0 |
Launch Clk | sysclk_in[R] |
Latch Clk | sysclk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sysclk_in | |||
0.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | w550013/SPI/cnt_4_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | w550013/SPI/cnt_4_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | w550013/SPI/sclk_r_s6/I1 |
2.403 | 0.814 | tINS | FF | 5 | w550013/SPI/sclk_r_s6/F |
3.115 | 0.711 | tNET | FF | 1 | w550013/SPI/n473_s6/I1 |
3.929 | 0.814 | tINS | FF | 3 | w550013/SPI/n473_s6/F |
4.640 | 0.711 | tNET | FF | 1 | w550013/SPI/n1234_s5/I0 |
5.405 | 0.765 | tINS | FF | 4 | w550013/SPI/n1234_s5/F |
6.116 | 0.711 | tNET | FF | 1 | w550013/SPI/n1231_s11/I1 |
6.931 | 0.814 | tINS | FF | 3 | w550013/SPI/n1231_s11/F |
7.642 | 0.711 | tNET | FF | 1 | w550013/SPI/n1233_s4/I1 |
8.457 | 0.814 | tINS | FF | 1 | w550013/SPI/n1233_s4/F |
9.168 | 0.711 | tNET | FF | 1 | w550013/SPI/n1233_s1/I2 |
9.777 | 0.609 | tINS | FF | 1 | w550013/SPI/n1233_s1/F |
10.488 | 0.711 | tNET | FF | 1 | w550013/SPI/num_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sysclk_in | |||
20.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
20.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | w550013/SPI/num_2_s0/CLK |
20.242 | -0.296 | tSu | 1 | w550013/SPI/num_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 4.631, 46.543%; route: 4.980, 50.044%; tC2Q: 0.340, 3.413% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:Slack | 9.849 |
Data Arrival Time | 10.393 |
Data Required Time | 20.242 |
From | w550013/SPI/cnt_4_s3 |
To | w550013/SPI/num_1_s0 |
Launch Clk | sysclk_in[R] |
Latch Clk | sysclk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sysclk_in | |||
0.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | w550013/SPI/cnt_4_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | w550013/SPI/cnt_4_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | w550013/SPI/sclk_r_s6/I1 |
2.403 | 0.814 | tINS | FF | 5 | w550013/SPI/sclk_r_s6/F |
3.115 | 0.711 | tNET | FF | 1 | w550013/SPI/n473_s6/I1 |
3.929 | 0.814 | tINS | FF | 3 | w550013/SPI/n473_s6/F |
4.640 | 0.711 | tNET | FF | 1 | w550013/SPI/n1230_s9/I1 |
5.455 | 0.814 | tINS | FF | 6 | w550013/SPI/n1230_s9/F |
6.166 | 0.711 | tNET | FF | 1 | w550013/SPI/n1234_s7/I1 |
6.980 | 0.814 | tINS | FF | 1 | w550013/SPI/n1234_s7/F |
7.692 | 0.711 | tNET | FF | 1 | w550013/SPI/n1234_s3/I3 |
8.156 | 0.464 | tINS | FF | 1 | w550013/SPI/n1234_s3/F |
8.867 | 0.711 | tNET | FF | 1 | w550013/SPI/n1234_s1/I1 |
9.681 | 0.814 | tINS | FF | 1 | w550013/SPI/n1234_s1/F |
10.393 | 0.711 | tNET | FF | 1 | w550013/SPI/num_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sysclk_in | |||
20.000 | 0.000 | tCL | RR | 1 | sysclk_in_ibuf/I |
20.000 | 0.000 | tINS | RR | 234 | sysclk_in_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | w550013/SPI/num_1_s0/CLK |
20.242 | -0.296 | tSu | 1 | w550013/SPI/num_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 4.536, 46.025%; route: 4.980, 50.529%; tC2Q: 0.340, 3.446% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |