Timing Messages

Report Title Timing Analysis Report
Design File /home/cnc/Desktop/GOWIN/Projects/W5500/impl/gwsynthesis/W5500.vg
Physical Constraints File /home/cnc/Desktop/GOWIN/Projects/W5500/src/pins.cst
Timing Constraint File ---
Tool Version V1.9.10
Part Number GW1NR-LV9QN88C7/I6
Device GW1NR-9
Device Version C
Created Time Fri Aug 2 05:49:42 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C7/I6
Hold Delay Model Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed 574
Numbers of Endpoints Analyzed 577
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
sysclk_in Base 20.000 50.000 0.000 10.000 sysclk_in_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sysclk_in 50.000(MHz) 114.156(MHz) 7 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
sysclk_in Setup 0.000 0
sysclk_in Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 11.240 w550013/cnt_10_0_s1/Q w550013/W5500_INIT_State_3_s0/CE sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.728
2 11.276 blink0/counter_2_s0/Q blink0/counter_30_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.428
3 11.295 blink0/counter_2_s0/Q blink0/counter_18_s1/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.409
4 11.330 w550013/SPI/cnt_5_s3/Q w550013/SPI/sel_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.373
5 11.330 w550013/SPI/cnt_5_s3/Q w550013/SPI/tx_ready_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.373
6 11.500 blink0/counter_2_s0/Q blink0/counter_16_s1/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.203
7 11.500 blink0/counter_2_s0/Q blink0/counter_28_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.203
8 11.569 w550013/SPI/num_6_s0/Q w550013/SPI/num_5_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.134
9 11.626 blink0/counter_2_s0/Q blink0/counter_31_s0/D sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.078
10 11.628 blink0/counter_2_s0/Q blink0/counter_5_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.339
11 11.628 blink0/counter_2_s0/Q blink0/counter_7_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.339
12 11.628 blink0/counter_2_s0/Q blink0/counter_8_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.339
13 11.628 blink0/counter_2_s0/Q blink0/counter_9_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.339
14 11.628 blink0/counter_2_s0/Q blink0/counter_17_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.339
15 11.638 blink0/counter_2_s0/Q blink0/counter_0_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.330
16 11.638 blink0/counter_2_s0/Q blink0/counter_28_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.330
17 11.689 blink0/counter_2_s0/Q blink0/counter_10_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
18 11.689 blink0/counter_2_s0/Q blink0/counter_15_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
19 11.689 blink0/counter_2_s0/Q blink0/counter_23_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
20 11.689 blink0/counter_2_s0/Q blink0/counter_25_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
21 11.689 blink0/counter_2_s0/Q blink0/counter_26_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
22 11.689 blink0/counter_2_s0/Q blink0/counter_27_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.279
23 11.694 blink0/counter_2_s0/Q blink0/counter_1_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.274
24 11.694 blink0/counter_2_s0/Q blink0/counter_2_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.274
25 11.694 blink0/counter_2_s0/Q blink0/counter_4_s0/RESET sysclk_in:[R] sysclk_in:[R] 20.000 0.000 8.274

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.524 w550013/SPI/cnt_6_s3/Q w550013/SPI/cnt_6_s3/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
2 0.524 w550013/SPI/num_bit_0_s0/Q w550013/SPI/num_bit_0_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
3 0.524 w550013/SPI/num_bit_10_s0/Q w550013/SPI/num_bit_10_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
4 0.524 w550013/SPI/num_bit_13_s0/Q w550013/SPI/num_bit_13_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
5 0.524 w550013/cnt_FP_0_s1/Q w550013/cnt_FP_0_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
6 0.524 w550013/cnt_MASK_0_s1/Q w550013/cnt_MASK_0_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
7 0.524 w550013/tx_data_16_s1/Q w550013/tx_data_16_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
8 0.524 w550013/tx_data_17_s1/Q w550013/tx_data_17_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
9 0.524 w550013/tx_data_23_s1/Q w550013/tx_data_23_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
10 0.524 w550013/tx_data_51_s1/Q w550013/tx_data_51_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
11 0.524 w550013/tx_data_60_s1/Q w550013/tx_data_60_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
12 0.524 w550013/tx_data_61_s1/Q w550013/tx_data_61_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
13 0.524 w550013/cnt_RETXTIME_2_s0/Q w550013/cnt_RETXTIME_2_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
14 0.524 w550013/cnt_TXBUFF_2_s0/Q w550013/cnt_TXBUFF_2_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
15 0.524 w550013/cnt_RXBUFF_2_s0/Q w550013/cnt_RXBUFF_2_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
16 0.524 w550013/cnt_IPADDR_2_s0/Q w550013/cnt_IPADDR_2_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
17 0.524 w550013/cnt_PHYADDR_2_s0/Q w550013/cnt_PHYADDR_2_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
18 0.524 w550013/Delay10_1_15_s0/Q w550013/Delay10_1_15_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
19 0.524 w550013/Delay10_1_22_s0/Q w550013/Delay10_1_22_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
20 0.524 w550013/Delay200_1_21_s0/Q w550013/Delay200_1_21_s0/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
21 0.524 blink0/counter_22_s1/Q blink0/counter_22_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
22 0.524 blink0/counter_20_s1/Q blink0/counter_20_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
23 0.524 blink0/counter_18_s1/Q blink0/counter_18_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
24 0.524 blink0/counter_12_s1/Q blink0/counter_12_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524
25 0.524 blink0/counter_6_s1/Q blink0/counter_6_s1/D sysclk_in:[R] sysclk_in:[R] 0.000 0.000 0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 8.094 9.020 0.926 Low Pulse Width sysclk_in blink0/counter_30_s0
2 8.094 9.020 0.926 Low Pulse Width sysclk_in blink0/counter_28_s0
3 8.094 9.020 0.926 Low Pulse Width sysclk_in blink0/counter_23_s0
4 8.094 9.020 0.926 Low Pulse Width sysclk_in blink0/counter_4_s0
5 8.094 9.020 0.926 Low Pulse Width sysclk_in blink0/counter_22_s1
6 8.094 9.020 0.926 Low Pulse Width sysclk_in w550013/Delay200_1_16_s0
7 8.094 9.020 0.926 Low Pulse Width sysclk_in w550013/W5500_INIT_State_0_s0
8 8.094 9.020 0.926 Low Pulse Width sysclk_in w550013/W5500_INIT_State_1_s0
9 8.094 9.020 0.926 Low Pulse Width sysclk_in w550013/Delay200_1_17_s0
10 8.094 9.020 0.926 Low Pulse Width sysclk_in w550013/W5500_INIT_State_2_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 11.240
Data Arrival Time 10.997
Data Required Time 22.237
From w550013/cnt_10_0_s1
To w550013/W5500_INIT_State_3_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R16C32[0][A] w550013/cnt_10_0_s1/CLK
2.608 0.340 tC2Q RF 5 R16C32[0][A] w550013/cnt_10_0_s1/Q
3.213 0.604 tNET FF 1 R16C30[2][A] w550013/n14399_s16/I0
4.027 0.814 tINS FF 8 R16C30[2][A] w550013/n14399_s16/F
5.479 1.452 tNET FF 1 R13C25[3][B] w550013/n2322_s26/I1
6.088 0.609 tINS FF 13 R13C25[3][B] w550013/n2322_s26/F
6.712 0.624 tNET FF 1 R14C24[3][B] w550013/n15360_s21/I3
7.321 0.609 tINS FF 2 R14C24[3][B] w550013/n15360_s21/F
8.281 0.959 tNET FF 1 R11C22[2][A] w550013/W5500_INIT_State_3_s6/I0
8.745 0.464 tINS FF 1 R11C22[2][A] w550013/W5500_INIT_State_3_s6/F
8.749 0.004 tNET FF 1 R11C22[1][A] w550013/W5500_INIT_State_3_s4/I1
9.358 0.609 tINS FF 3 R11C22[1][A] w550013/W5500_INIT_State_3_s4/F
9.961 0.603 tNET FF 1 R12C21[3][A] w550013/W5500_INIT_State_3_s5/I3
10.747 0.786 tINS FR 1 R12C21[3][A] w550013/W5500_INIT_State_3_s5/F
10.997 0.249 tNET RR 1 R12C21[0][B] w550013/W5500_INIT_State_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R12C21[0][B] w550013/W5500_INIT_State_3_s0/CLK
22.237 -0.032 tSu 1 R12C21[0][B] w550013/W5500_INIT_State_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.892, 44.590%; route: 4.496, 51.518%; tC2Q: 0.340, 3.891%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path2

Path Summary:

Slack 11.276
Data Arrival Time 10.697
Data Required Time 21.972
From blink0/counter_2_s0
To blink0/counter_30_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.259 0.814 tINS FF 5 R13C37[3][A] blink0/n6_s1/F
9.882 0.624 tNET FF 1 R13C38[1][A] blink0/n10_s5/I0
10.697 0.814 tINS FF 1 R13C38[1][A] blink0/n10_s5/F
10.697 0.000 tNET FF 1 R13C38[1][A] blink0/counter_30_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C38[1][A] blink0/counter_30_s0/CLK
21.972 -0.296 tSu 1 R13C38[1][A] blink0/counter_30_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.577, 54.309%; route: 3.511, 41.662%; tC2Q: 0.340, 4.030%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path3

Path Summary:

Slack 11.295
Data Arrival Time 10.677
Data Required Time 21.972
From blink0/counter_2_s0
To blink0/counter_18_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R14C37[3][A] blink0/counter_16_s4/I2
9.259 0.814 tINS FF 3 R14C37[3][A] blink0/counter_16_s4/F
9.863 0.604 tNET FF 1 R15C38[1][A] blink0/counter_18_s3/I1
10.677 0.814 tINS FF 1 R15C38[1][A] blink0/counter_18_s3/F
10.677 0.000 tNET FF 1 R15C38[1][A] blink0/counter_18_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C38[1][A] blink0/counter_18_s1/CLK
21.972 -0.296 tSu 1 R15C38[1][A] blink0/counter_18_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.577, 54.435%; route: 3.492, 41.526%; tC2Q: 0.340, 4.039%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path4

Path Summary:

Slack 11.330
Data Arrival Time 10.642
Data Required Time 21.972
From w550013/SPI/cnt_5_s3
To w550013/SPI/sel_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R11C36[0][A] w550013/SPI/cnt_5_s3/CLK
2.608 0.340 tC2Q RR 4 R11C36[0][A] w550013/SPI/cnt_5_s3/Q
2.924 0.315 tNET RR 1 R12C36[2][B] w550013/SPI/sclk_r_s6/I2
3.738 0.814 tINS RF 5 R12C36[2][B] w550013/SPI/sclk_r_s6/F
4.714 0.976 tNET FF 1 R13C36[1][B] w550013/SPI/n473_s6/I1
5.528 0.814 tINS FF 3 R13C36[1][B] w550013/SPI/n473_s6/F
6.132 0.603 tNET FF 1 R12C35[2][B] w550013/SPI/n1234_s5/I0
6.741 0.609 tINS FF 4 R12C35[2][B] w550013/SPI/n1234_s5/F
7.349 0.608 tNET FF 1 R13C34[1][B] w550013/SPI/n473_s4/I0
7.958 0.609 tINS FF 1 R13C34[1][B] w550013/SPI/n473_s4/F
7.962 0.004 tNET FF 1 R13C34[1][A] w550013/SPI/n473_s9/I3
8.777 0.814 tINS FF 3 R13C34[1][A] w550013/SPI/n473_s9/F
9.877 1.101 tNET FF 1 R15C30[0][A] w550013/SPI/n1220_s2/I0
10.642 0.765 tINS FF 1 R15C30[0][A] w550013/SPI/n1220_s2/F
10.642 0.000 tNET FF 1 R15C30[0][A] w550013/SPI/sel_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C30[0][A] w550013/SPI/sel_s0/CLK
21.972 -0.296 tSu 1 R15C30[0][A] w550013/SPI/sel_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.426, 52.859%; route: 3.608, 43.085%; tC2Q: 0.340, 4.056%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path5

Path Summary:

Slack 11.330
Data Arrival Time 10.642
Data Required Time 21.972
From w550013/SPI/cnt_5_s3
To w550013/SPI/tx_ready_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R11C36[0][A] w550013/SPI/cnt_5_s3/CLK
2.608 0.340 tC2Q RR 4 R11C36[0][A] w550013/SPI/cnt_5_s3/Q
2.924 0.315 tNET RR 1 R12C36[2][B] w550013/SPI/sclk_r_s6/I2
3.738 0.814 tINS RF 5 R12C36[2][B] w550013/SPI/sclk_r_s6/F
4.714 0.976 tNET FF 1 R13C36[1][B] w550013/SPI/n473_s6/I1
5.528 0.814 tINS FF 3 R13C36[1][B] w550013/SPI/n473_s6/F
6.132 0.603 tNET FF 1 R12C35[2][B] w550013/SPI/n1234_s5/I0
6.741 0.609 tINS FF 4 R12C35[2][B] w550013/SPI/n1234_s5/F
7.349 0.608 tNET FF 1 R13C34[1][B] w550013/SPI/n473_s4/I0
7.958 0.609 tINS FF 1 R13C34[1][B] w550013/SPI/n473_s4/F
7.962 0.004 tNET FF 1 R13C34[1][A] w550013/SPI/n473_s9/I3
8.777 0.814 tINS FF 3 R13C34[1][A] w550013/SPI/n473_s9/F
9.877 1.101 tNET FF 1 R15C30[0][B] w550013/SPI/n473_s0/I2
10.642 0.765 tINS FF 1 R15C30[0][B] w550013/SPI/n473_s0/F
10.642 0.000 tNET FF 1 R15C30[0][B] w550013/SPI/tx_ready_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C30[0][B] w550013/SPI/tx_ready_s0/CLK
21.972 -0.296 tSu 1 R15C30[0][B] w550013/SPI/tx_ready_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.426, 52.859%; route: 3.608, 43.085%; tC2Q: 0.340, 4.056%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path6

Path Summary:

Slack 11.500
Data Arrival Time 10.472
Data Required Time 21.972
From blink0/counter_2_s0
To blink0/counter_16_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R14C37[3][A] blink0/counter_16_s4/I2
9.259 0.814 tINS FF 3 R14C37[3][A] blink0/counter_16_s4/F
9.863 0.604 tNET FF 1 R15C38[1][B] blink0/counter_16_s3/I1
10.472 0.609 tINS FF 1 R15C38[1][B] blink0/counter_16_s3/F
10.472 0.000 tNET FF 1 R15C38[1][B] blink0/counter_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C38[1][B] blink0/counter_16_s1/CLK
21.972 -0.296 tSu 1 R15C38[1][B] blink0/counter_16_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.372, 53.295%; route: 3.492, 42.565%; tC2Q: 0.340, 4.140%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path7

Path Summary:

Slack 11.500
Data Arrival Time 10.472
Data Required Time 21.972
From blink0/counter_2_s0
To blink0/counter_28_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.259 0.814 tINS FF 5 R13C37[3][A] blink0/n6_s1/F
9.863 0.604 tNET FF 1 R14C38[0][A] blink0/n12_s4/I1
10.472 0.609 tINS FF 1 R14C38[0][A] blink0/n12_s4/F
10.472 0.000 tNET FF 1 R14C38[0][A] blink0/counter_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R14C38[0][A] blink0/counter_28_s0/CLK
21.972 -0.296 tSu 1 R14C38[0][A] blink0/counter_28_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.372, 53.295%; route: 3.492, 42.565%; tC2Q: 0.340, 4.140%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path8

Path Summary:

Slack 11.569
Data Arrival Time 10.403
Data Required Time 21.972
From w550013/SPI/num_6_s0
To w550013/SPI/num_5_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C33[1][B] w550013/SPI/num_6_s0/CLK
2.608 0.340 tC2Q RF 9 R15C33[1][B] w550013/SPI/num_6_s0/Q
3.348 0.740 tNET FF 1 R13C35[0][B] w550013/SPI/n1197_s29/I2
4.162 0.814 tINS FF 4 R13C35[0][B] w550013/SPI/n1197_s29/F
4.766 0.603 tNET FF 1 R14C33[1][A] w550013/SPI/n1234_s8/I3
5.580 0.814 tINS FF 2 R14C33[1][A] w550013/SPI/n1234_s8/F
6.192 0.612 tNET FF 1 R13C33[0][A] w550013/SPI/n1234_s11/I3
7.006 0.814 tINS FF 3 R13C33[0][A] w550013/SPI/n1234_s11/F
7.615 0.608 tNET FF 1 R12C34[1][B] w550013/SPI/n1230_s6/I0
8.224 0.609 tINS FF 1 R12C34[1][B] w550013/SPI/n1230_s6/F
8.820 0.596 tNET FF 1 R11C35[2][B] w550013/SPI/n1230_s2/I2
9.634 0.814 tINS FF 1 R11C35[2][B] w550013/SPI/n1230_s2/F
9.638 0.004 tNET FF 1 R11C35[1][B] w550013/SPI/n1230_s1/I0
10.403 0.765 tINS FF 1 R11C35[1][B] w550013/SPI/n1230_s1/F
10.403 0.000 tNET FF 1 R11C35[1][B] w550013/SPI/num_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R11C35[1][B] w550013/SPI/num_5_s0/CLK
21.972 -0.296 tSu 1 R11C35[1][B] w550013/SPI/num_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.631, 56.935%; route: 3.163, 38.889%; tC2Q: 0.340, 4.175%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path9

Path Summary:

Slack 11.626
Data Arrival Time 10.346
Data Required Time 21.972
From blink0/counter_2_s0
To blink0/counter_31_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.259 0.814 tINS FF 5 R13C37[3][A] blink0/n6_s1/F
9.882 0.624 tNET FF 1 R13C38[1][B] blink0/n9_s3/I1
10.346 0.464 tINS FF 1 R13C38[1][B] blink0/n9_s3/F
10.346 0.000 tNET FF 1 R13C38[1][B] blink0/counter_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C38[1][B] blink0/counter_31_s0/CLK
21.972 -0.296 tSu 1 R13C38[1][B] blink0/counter_31_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.227, 52.326%; route: 3.511, 43.469%; tC2Q: 0.340, 4.205%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path10

Path Summary:

Slack 11.628
Data Arrival Time 10.608
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_5_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.608 0.598 tNET RR 1 R15C37[1][B] blink0/counter_5_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C37[1][B] blink0/counter_5_s0/CLK
22.237 -0.032 tSu 1 R15C37[1][B] blink0/counter_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.336%; route: 3.802, 45.591%; tC2Q: 0.340, 4.073%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path11

Path Summary:

Slack 11.628
Data Arrival Time 10.608
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_7_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.608 0.598 tNET RR 1 R15C37[1][A] blink0/counter_7_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C37[1][A] blink0/counter_7_s0/CLK
22.237 -0.032 tSu 1 R15C37[1][A] blink0/counter_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.336%; route: 3.802, 45.591%; tC2Q: 0.340, 4.073%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path12

Path Summary:

Slack 11.628
Data Arrival Time 10.608
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_8_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.608 0.598 tNET RR 1 R15C37[0][B] blink0/counter_8_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C37[0][B] blink0/counter_8_s0/CLK
22.237 -0.032 tSu 1 R15C37[0][B] blink0/counter_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.336%; route: 3.802, 45.591%; tC2Q: 0.340, 4.073%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path13

Path Summary:

Slack 11.628
Data Arrival Time 10.608
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_9_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.608 0.598 tNET RR 1 R15C37[0][A] blink0/counter_9_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C37[0][A] blink0/counter_9_s0/CLK
22.237 -0.032 tSu 1 R15C37[0][A] blink0/counter_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.336%; route: 3.802, 45.591%; tC2Q: 0.340, 4.073%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path14

Path Summary:

Slack 11.628
Data Arrival Time 10.608
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_17_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.608 0.598 tNET RR 1 R15C37[2][B] blink0/counter_17_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C37[2][B] blink0/counter_17_s0/CLK
22.237 -0.032 tSu 1 R15C37[2][B] blink0/counter_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.336%; route: 3.802, 45.591%; tC2Q: 0.340, 4.073%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path15

Path Summary:

Slack 11.638
Data Arrival Time 10.598
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_0_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.598 0.589 tNET RR 1 R14C38[0][B] blink0/counter_0_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R14C38[0][B] blink0/counter_0_s0/CLK
22.237 -0.032 tSu 1 R14C38[0][B] blink0/counter_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.395%; route: 3.792, 45.528%; tC2Q: 0.340, 4.077%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path16

Path Summary:

Slack 11.638
Data Arrival Time 10.598
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_28_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.598 0.589 tNET RR 1 R14C38[0][A] blink0/counter_28_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R14C38[0][A] blink0/counter_28_s0/CLK
22.237 -0.032 tSu 1 R14C38[0][A] blink0/counter_28_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.395%; route: 3.792, 45.528%; tC2Q: 0.340, 4.077%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path17

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_10_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[2][B] blink0/counter_10_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[2][B] blink0/counter_10_s0/CLK
22.237 -0.032 tSu 1 R13C37[2][B] blink0/counter_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path18

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_15_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[0][A] blink0/counter_15_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[0][A] blink0/counter_15_s0/CLK
22.237 -0.032 tSu 1 R13C37[0][A] blink0/counter_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path19

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_23_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[2][A] blink0/counter_23_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[2][A] blink0/counter_23_s0/CLK
22.237 -0.032 tSu 1 R13C37[2][A] blink0/counter_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path20

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_25_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[1][B] blink0/counter_25_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[1][B] blink0/counter_25_s0/CLK
22.237 -0.032 tSu 1 R13C37[1][B] blink0/counter_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path21

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_26_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[1][A] blink0/counter_26_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[1][A] blink0/counter_26_s0/CLK
22.237 -0.032 tSu 1 R13C37[1][A] blink0/counter_26_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path22

Path Summary:

Slack 11.689
Data Arrival Time 10.548
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_27_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.548 0.538 tNET RR 1 R13C37[0][B] blink0/counter_27_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R13C37[0][B] blink0/counter_27_s0/CLK
22.237 -0.032 tSu 1 R13C37[0][B] blink0/counter_27_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.701%; route: 3.742, 45.197%; tC2Q: 0.340, 4.102%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path23

Path Summary:

Slack 11.694
Data Arrival Time 10.543
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_1_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.543 0.533 tNET RR 1 R15C38[0][A] blink0/counter_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C38[0][A] blink0/counter_1_s0/CLK
22.237 -0.032 tSu 1 R15C38[0][A] blink0/counter_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.735%; route: 3.737, 45.160%; tC2Q: 0.340, 4.105%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path24

Path Summary:

Slack 11.694
Data Arrival Time 10.543
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.543 0.533 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
22.237 -0.032 tSu 1 R15C38[0][B] blink0/counter_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.735%; route: 3.737, 45.160%; tC2Q: 0.340, 4.105%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path25

Path Summary:

Slack 11.694
Data Arrival Time 10.543
Data Required Time 22.237
From blink0/counter_2_s0
To blink0/counter_4_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
2.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
2.269 0.181 tNET RR 1 R15C38[0][B] blink0/counter_2_s0/CLK
2.608 0.340 tC2Q RF 3 R15C38[0][B] blink0/counter_2_s0/Q
2.977 0.369 tNET FF 1 R13C38[0][A] blink0/counter_6_s4/I2
3.791 0.814 tINS FF 4 R13C38[0][A] blink0/counter_6_s4/F
4.399 0.608 tNET FF 1 R14C37[2][B] blink0/n33_s5/I3
5.159 0.760 tINS FR 4 R14C37[2][B] blink0/n33_s5/F
5.478 0.319 tNET RR 1 R15C37[2][A] blink0/counter_11_s4/I3
6.243 0.765 tINS RF 4 R15C37[2][A] blink0/counter_11_s4/F
7.209 0.966 tNET FF 1 R12C38[2][B] blink0/counter_13_s4/I3
7.818 0.609 tINS FF 13 R12C38[2][B] blink0/counter_13_s4/F
8.444 0.626 tNET FF 1 R13C37[3][A] blink0/n6_s1/I3
9.231 0.786 tINS FR 5 R13C37[3][A] blink0/n6_s1/F
9.547 0.316 tNET RR 1 R13C38[2][B] blink0/n6_s0/I2
10.010 0.463 tINS RR 21 R13C38[2][B] blink0/n6_s0/F
10.543 0.533 tNET RR 1 R15C38[2][B] blink0/counter_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
22.088 2.088 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
22.269 0.181 tNET RR 1 R15C38[2][B] blink0/counter_4_s0/CLK
22.237 -0.032 tSu 1 R15C38[2][B] blink0/counter_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.198, 50.735%; route: 3.737, 45.160%; tC2Q: 0.340, 4.105%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/SPI/cnt_6_s3
To w550013/SPI/cnt_6_s3
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C36[1][A] w550013/SPI/cnt_6_s3/CLK
1.776 0.247 tC2Q RR 3 R12C36[1][A] w550013/SPI/cnt_6_s3/Q
1.778 0.002 tNET RR 1 R12C36[1][A] w550013/SPI/n47_s1/I3
2.053 0.276 tINS RF 1 R12C36[1][A] w550013/SPI/n47_s1/F
2.053 0.000 tNET FF 1 R12C36[1][A] w550013/SPI/cnt_6_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C36[1][A] w550013/SPI/cnt_6_s3/CLK
1.529 0.000 tHld 1 R12C36[1][A] w550013/SPI/cnt_6_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/SPI/num_bit_0_s0
To w550013/SPI/num_bit_0_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C33[0][A] w550013/SPI/num_bit_0_s0/CLK
1.776 0.247 tC2Q RR 6 R9C33[0][A] w550013/SPI/num_bit_0_s0/Q
1.778 0.002 tNET RR 1 R9C33[0][A] w550013/SPI/n573_s2/I2
2.053 0.276 tINS RF 1 R9C33[0][A] w550013/SPI/n573_s2/F
2.053 0.000 tNET FF 1 R9C33[0][A] w550013/SPI/num_bit_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C33[0][A] w550013/SPI/num_bit_0_s0/CLK
1.529 0.000 tHld 1 R9C33[0][A] w550013/SPI/num_bit_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/SPI/num_bit_10_s0
To w550013/SPI/num_bit_10_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C36[0][A] w550013/SPI/num_bit_10_s0/CLK
1.776 0.247 tC2Q RR 5 R9C36[0][A] w550013/SPI/num_bit_10_s0/Q
1.778 0.002 tNET RR 1 R9C36[0][A] w550013/SPI/n563_s2/I0
2.053 0.276 tINS RF 1 R9C36[0][A] w550013/SPI/n563_s2/F
2.053 0.000 tNET FF 1 R9C36[0][A] w550013/SPI/num_bit_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C36[0][A] w550013/SPI/num_bit_10_s0/CLK
1.529 0.000 tHld 1 R9C36[0][A] w550013/SPI/num_bit_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/SPI/num_bit_13_s0
To w550013/SPI/num_bit_13_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C35[1][A] w550013/SPI/num_bit_13_s0/CLK
1.776 0.247 tC2Q RR 2 R9C35[1][A] w550013/SPI/num_bit_13_s0/Q
1.778 0.002 tNET RR 1 R9C35[1][A] w550013/SPI/n560_s2/I3
2.053 0.276 tINS RF 1 R9C35[1][A] w550013/SPI/n560_s2/F
2.053 0.000 tNET FF 1 R9C35[1][A] w550013/SPI/num_bit_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C35[1][A] w550013/SPI/num_bit_13_s0/CLK
1.529 0.000 tHld 1 R9C35[1][A] w550013/SPI/num_bit_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_FP_0_s1
To w550013/cnt_FP_0_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C23[1][A] w550013/cnt_FP_0_s1/CLK
1.776 0.247 tC2Q RR 5 R15C23[1][A] w550013/cnt_FP_0_s1/Q
1.778 0.002 tNET RR 1 R15C23[1][A] w550013/n448_s3/I0
2.053 0.276 tINS RF 1 R15C23[1][A] w550013/n448_s3/F
2.053 0.000 tNET FF 1 R15C23[1][A] w550013/cnt_FP_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C23[1][A] w550013/cnt_FP_0_s1/CLK
1.529 0.000 tHld 1 R15C23[1][A] w550013/cnt_FP_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path6

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_MASK_0_s1
To w550013/cnt_MASK_0_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C21[0][A] w550013/cnt_MASK_0_s1/CLK
1.776 0.247 tC2Q RR 4 R14C21[0][A] w550013/cnt_MASK_0_s1/Q
1.778 0.002 tNET RR 1 R14C21[0][A] w550013/n365_s3/I1
2.053 0.276 tINS RF 1 R14C21[0][A] w550013/n365_s3/F
2.053 0.000 tNET FF 1 R14C21[0][A] w550013/cnt_MASK_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C21[0][A] w550013/cnt_MASK_0_s1/CLK
1.529 0.000 tHld 1 R14C21[0][A] w550013/cnt_MASK_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path7

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_16_s1
To w550013/tx_data_16_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C24[1][A] w550013/tx_data_16_s1/CLK
1.776 0.247 tC2Q RR 2 R9C24[1][A] w550013/tx_data_16_s1/Q
1.778 0.002 tNET RR 1 R9C24[1][A] w550013/n14457_s27/I1
2.053 0.276 tINS RF 1 R9C24[1][A] w550013/n14457_s27/F
2.053 0.000 tNET FF 1 R9C24[1][A] w550013/tx_data_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C24[1][A] w550013/tx_data_16_s1/CLK
1.529 0.000 tHld 1 R9C24[1][A] w550013/tx_data_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path8

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_17_s1
To w550013/tx_data_17_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C24[0][A] w550013/tx_data_17_s1/CLK
1.776 0.247 tC2Q RR 2 R11C24[0][A] w550013/tx_data_17_s1/Q
1.778 0.002 tNET RR 1 R11C24[0][A] w550013/n14456_s24/I1
2.053 0.276 tINS RF 1 R11C24[0][A] w550013/n14456_s24/F
2.053 0.000 tNET FF 1 R11C24[0][A] w550013/tx_data_17_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C24[0][A] w550013/tx_data_17_s1/CLK
1.529 0.000 tHld 1 R11C24[0][A] w550013/tx_data_17_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path9

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_23_s1
To w550013/tx_data_23_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C24[0][A] w550013/tx_data_23_s1/CLK
1.776 0.247 tC2Q RR 2 R15C24[0][A] w550013/tx_data_23_s1/Q
1.778 0.002 tNET RR 1 R15C24[0][A] w550013/n14451_s24/I0
2.053 0.276 tINS RF 1 R15C24[0][A] w550013/n14451_s24/F
2.053 0.000 tNET FF 1 R15C24[0][A] w550013/tx_data_23_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C24[0][A] w550013/tx_data_23_s1/CLK
1.529 0.000 tHld 1 R15C24[0][A] w550013/tx_data_23_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path10

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_51_s1
To w550013/tx_data_51_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C25[1][A] w550013/tx_data_51_s1/CLK
1.776 0.247 tC2Q RR 3 R9C25[1][A] w550013/tx_data_51_s1/Q
1.778 0.002 tNET RR 1 R9C25[1][A] w550013/n14422_s26/I1
2.053 0.276 tINS RF 1 R9C25[1][A] w550013/n14422_s26/F
2.053 0.000 tNET FF 1 R9C25[1][A] w550013/tx_data_51_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C25[1][A] w550013/tx_data_51_s1/CLK
1.529 0.000 tHld 1 R9C25[1][A] w550013/tx_data_51_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path11

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_60_s1
To w550013/tx_data_60_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C22[0][A] w550013/tx_data_60_s1/CLK
1.776 0.247 tC2Q RR 3 R11C22[0][A] w550013/tx_data_60_s1/Q
1.778 0.002 tNET RR 1 R11C22[0][A] w550013/n14413_s23/I1
2.053 0.276 tINS RF 1 R11C22[0][A] w550013/n14413_s23/F
2.053 0.000 tNET FF 1 R11C22[0][A] w550013/tx_data_60_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C22[0][A] w550013/tx_data_60_s1/CLK
1.529 0.000 tHld 1 R11C22[0][A] w550013/tx_data_60_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path12

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/tx_data_61_s1
To w550013/tx_data_61_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C23[0][A] w550013/tx_data_61_s1/CLK
1.776 0.247 tC2Q RR 3 R12C23[0][A] w550013/tx_data_61_s1/Q
1.778 0.002 tNET RR 1 R12C23[0][A] w550013/n14412_s25/I1
2.053 0.276 tINS RF 1 R12C23[0][A] w550013/n14412_s25/F
2.053 0.000 tNET FF 1 R12C23[0][A] w550013/tx_data_61_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C23[0][A] w550013/tx_data_61_s1/CLK
1.529 0.000 tHld 1 R12C23[0][A] w550013/tx_data_61_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path13

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_RETXTIME_2_s0
To w550013/cnt_RETXTIME_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C20[1][A] w550013/cnt_RETXTIME_2_s0/CLK
1.776 0.247 tC2Q RR 2 R14C20[1][A] w550013/cnt_RETXTIME_2_s0/Q
1.778 0.002 tNET RR 1 R14C20[1][A] w550013/n423_s0/I2
2.053 0.276 tINS RF 1 R14C20[1][A] w550013/n423_s0/F
2.053 0.000 tNET FF 1 R14C20[1][A] w550013/cnt_RETXTIME_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C20[1][A] w550013/cnt_RETXTIME_2_s0/CLK
1.529 0.000 tHld 1 R14C20[1][A] w550013/cnt_RETXTIME_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path14

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_TXBUFF_2_s0
To w550013/cnt_TXBUFF_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C19[0][A] w550013/cnt_TXBUFF_2_s0/CLK
1.776 0.247 tC2Q RR 2 R14C19[0][A] w550013/cnt_TXBUFF_2_s0/Q
1.778 0.002 tNET RR 1 R14C19[0][A] w550013/n411_s0/I2
2.053 0.276 tINS RF 1 R14C19[0][A] w550013/n411_s0/F
2.053 0.000 tNET FF 1 R14C19[0][A] w550013/cnt_TXBUFF_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C19[0][A] w550013/cnt_TXBUFF_2_s0/CLK
1.529 0.000 tHld 1 R14C19[0][A] w550013/cnt_TXBUFF_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path15

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_RXBUFF_2_s0
To w550013/cnt_RXBUFF_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C21[0][A] w550013/cnt_RXBUFF_2_s0/CLK
1.776 0.247 tC2Q RR 2 R9C21[0][A] w550013/cnt_RXBUFF_2_s0/Q
1.778 0.002 tNET RR 1 R9C21[0][A] w550013/n400_s0/I2
2.053 0.276 tINS RF 1 R9C21[0][A] w550013/n400_s0/F
2.053 0.000 tNET FF 1 R9C21[0][A] w550013/cnt_RXBUFF_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C21[0][A] w550013/cnt_RXBUFF_2_s0/CLK
1.529 0.000 tHld 1 R9C21[0][A] w550013/cnt_RXBUFF_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path16

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_IPADDR_2_s0
To w550013/cnt_IPADDR_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C20[1][A] w550013/cnt_IPADDR_2_s0/CLK
1.776 0.247 tC2Q RR 2 R11C20[1][A] w550013/cnt_IPADDR_2_s0/Q
1.778 0.002 tNET RR 1 R11C20[1][A] w550013/n387_s0/I2
2.053 0.276 tINS RF 1 R11C20[1][A] w550013/n387_s0/F
2.053 0.000 tNET FF 1 R11C20[1][A] w550013/cnt_IPADDR_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C20[1][A] w550013/cnt_IPADDR_2_s0/CLK
1.529 0.000 tHld 1 R11C20[1][A] w550013/cnt_IPADDR_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path17

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/cnt_PHYADDR_2_s0
To w550013/cnt_PHYADDR_2_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C20[1][A] w550013/cnt_PHYADDR_2_s0/CLK
1.776 0.247 tC2Q RR 2 R9C20[1][A] w550013/cnt_PHYADDR_2_s0/Q
1.778 0.002 tNET RR 1 R9C20[1][A] w550013/n375_s0/I2
2.053 0.276 tINS RF 1 R9C20[1][A] w550013/n375_s0/F
2.053 0.000 tNET FF 1 R9C20[1][A] w550013/cnt_PHYADDR_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C20[1][A] w550013/cnt_PHYADDR_2_s0/CLK
1.529 0.000 tHld 1 R9C20[1][A] w550013/cnt_PHYADDR_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path18

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/Delay10_1_15_s0
To w550013/Delay10_1_15_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C19[1][A] w550013/Delay10_1_15_s0/CLK
1.776 0.247 tC2Q RR 4 R9C19[1][A] w550013/Delay10_1_15_s0/Q
1.778 0.002 tNET RR 1 R9C19[1][A] w550013/n236_s1/I0
2.053 0.276 tINS RF 1 R9C19[1][A] w550013/n236_s1/F
2.053 0.000 tNET FF 1 R9C19[1][A] w550013/Delay10_1_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R9C19[1][A] w550013/Delay10_1_15_s0/CLK
1.529 0.000 tHld 1 R9C19[1][A] w550013/Delay10_1_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path19

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/Delay10_1_22_s0
To w550013/Delay10_1_22_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C19[0][A] w550013/Delay10_1_22_s0/CLK
1.776 0.247 tC2Q RR 3 R11C19[0][A] w550013/Delay10_1_22_s0/Q
1.778 0.002 tNET RR 1 R11C19[0][A] w550013/n229_s1/I0
2.053 0.276 tINS RF 1 R11C19[0][A] w550013/n229_s1/F
2.053 0.000 tNET FF 1 R11C19[0][A] w550013/Delay10_1_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C19[0][A] w550013/Delay10_1_22_s0/CLK
1.529 0.000 tHld 1 R11C19[0][A] w550013/Delay10_1_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path20

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From w550013/Delay200_1_21_s0
To w550013/Delay200_1_21_s0
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C26[1][A] w550013/Delay200_1_21_s0/CLK
1.776 0.247 tC2Q RR 3 R11C26[1][A] w550013/Delay200_1_21_s0/Q
1.778 0.002 tNET RR 1 R11C26[1][A] w550013/n152_s1/I2
2.053 0.276 tINS RF 1 R11C26[1][A] w550013/n152_s1/F
2.053 0.000 tNET FF 1 R11C26[1][A] w550013/Delay200_1_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R11C26[1][A] w550013/Delay200_1_21_s0/CLK
1.529 0.000 tHld 1 R11C26[1][A] w550013/Delay200_1_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path21

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From blink0/counter_22_s1
To blink0/counter_22_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C38[1][A] blink0/counter_22_s1/CLK
1.776 0.247 tC2Q RR 2 R14C38[1][A] blink0/counter_22_s1/Q
1.778 0.002 tNET RR 1 R14C38[1][A] blink0/counter_22_s3/I2
2.053 0.276 tINS RF 1 R14C38[1][A] blink0/counter_22_s3/F
2.053 0.000 tNET FF 1 R14C38[1][A] blink0/counter_22_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C38[1][A] blink0/counter_22_s1/CLK
1.529 0.000 tHld 1 R14C38[1][A] blink0/counter_22_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path22

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From blink0/counter_20_s1
To blink0/counter_20_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C38[1][A] blink0/counter_20_s1/CLK
1.776 0.247 tC2Q RR 3 R12C38[1][A] blink0/counter_20_s1/Q
1.778 0.002 tNET RR 1 R12C38[1][A] blink0/counter_20_s3/I3
2.053 0.276 tINS RF 1 R12C38[1][A] blink0/counter_20_s3/F
2.053 0.000 tNET FF 1 R12C38[1][A] blink0/counter_20_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C38[1][A] blink0/counter_20_s1/CLK
1.529 0.000 tHld 1 R12C38[1][A] blink0/counter_20_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path23

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From blink0/counter_18_s1
To blink0/counter_18_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C38[1][A] blink0/counter_18_s1/CLK
1.776 0.247 tC2Q RR 2 R15C38[1][A] blink0/counter_18_s1/Q
1.778 0.002 tNET RR 1 R15C38[1][A] blink0/counter_18_s3/I2
2.053 0.276 tINS RF 1 R15C38[1][A] blink0/counter_18_s3/F
2.053 0.000 tNET FF 1 R15C38[1][A] blink0/counter_18_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R15C38[1][A] blink0/counter_18_s1/CLK
1.529 0.000 tHld 1 R15C38[1][A] blink0/counter_18_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path24

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From blink0/counter_12_s1
To blink0/counter_12_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C38[0][A] blink0/counter_12_s1/CLK
1.776 0.247 tC2Q RR 2 R12C38[0][A] blink0/counter_12_s1/Q
1.778 0.002 tNET RR 1 R12C38[0][A] blink0/counter_12_s3/I3
2.053 0.276 tINS RF 1 R12C38[0][A] blink0/counter_12_s3/F
2.053 0.000 tNET FF 1 R12C38[0][A] blink0/counter_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R12C38[0][A] blink0/counter_12_s1/CLK
1.529 0.000 tHld 1 R12C38[0][A] blink0/counter_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path25

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From blink0/counter_6_s1
To blink0/counter_6_s1
Launch Clk sysclk_in:[R]
Latch Clk sysclk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C37[0][A] blink0/counter_6_s1/CLK
1.776 0.247 tC2Q RR 2 R14C37[0][A] blink0/counter_6_s1/Q
1.778 0.002 tNET RR 1 R14C37[0][A] blink0/counter_6_s3/I3
2.053 0.276 tINS RF 1 R14C37[0][A] blink0/counter_6_s3/F
2.053 0.000 tNET FF 1 R14C37[0][A] blink0/counter_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sysclk_in
0.000 0.000 tCL RR 1 IOR17[A] sysclk_in_ibuf/I
1.392 1.392 tINS RR 234 IOR17[A] sysclk_in_ibuf/O
1.529 0.137 tNET RR 1 R14C37[0][A] blink0/counter_6_s1/CLK
1.529 0.000 tHld 1 R14C37[0][A] blink0/counter_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: blink0/counter_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF blink0/counter_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR blink0/counter_30_s0/CLK

MPW2

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: blink0/counter_28_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF blink0/counter_28_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR blink0/counter_28_s0/CLK

MPW3

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: blink0/counter_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF blink0/counter_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR blink0/counter_23_s0/CLK

MPW4

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: blink0/counter_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF blink0/counter_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR blink0/counter_4_s0/CLK

MPW5

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: blink0/counter_22_s1

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF blink0/counter_22_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR blink0/counter_22_s1/CLK

MPW6

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: w550013/Delay200_1_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF w550013/Delay200_1_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR w550013/Delay200_1_16_s0/CLK

MPW7

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: w550013/W5500_INIT_State_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF w550013/W5500_INIT_State_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR w550013/W5500_INIT_State_0_s0/CLK

MPW8

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: w550013/W5500_INIT_State_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF w550013/W5500_INIT_State_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR w550013/W5500_INIT_State_1_s0/CLK

MPW9

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: w550013/Delay200_1_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF w550013/Delay200_1_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR w550013/Delay200_1_17_s0/CLK

MPW10

MPW Summary:

Slack: 8.094
Actual Width: 9.020
Required Width: 0.926
Type: Low Pulse Width
Clock: sysclk_in
Objects: w550013/W5500_INIT_State_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 sysclk_in
10.000 0.000 tCL FF sysclk_in_ibuf/I
12.314 2.314 tINS FF sysclk_in_ibuf/O
12.509 0.195 tNET FF w550013/W5500_INIT_State_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 sysclk_in
20.000 0.000 tCL RR sysclk_in_ibuf/I
21.392 1.392 tINS RR sysclk_in_ibuf/O
21.529 0.137 tNET RR w550013/W5500_INIT_State_2_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
234 sysclk_in_d 11.240 0.195
29 W5500_INIT_State[1] 13.398 1.369
28 W5500_INIT_State[0] 13.434 1.369
27 num[0] 12.100 1.491
27 W5500_INIT_State[3] 13.922 1.357
26 tx_data_50_13 12.722 1.483
25 num[1] 12.439 1.398
24 n251_10 16.383 1.024
24 n14412_36 12.938 1.133
24 num_bit_13_6 11.897 1.359

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C37 81.94%
R9C20 79.17%
R9C32 77.78%
R11C36 77.78%
R9C30 77.78%
R9C31 76.39%
R13C25 75.00%
R11C24 75.00%
R15C30 73.61%
R14C21 73.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command