Parameters:
Owner Type Dir Value Name
26 bit RW FALSE hm2_7i95.0.encoder.00.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.00.filter
26 bit RW FALSE hm2_7i95.0.encoder.00.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.00.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.00.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.00.scale
26 bit RW FALSE hm2_7i95.0.encoder.00.sel0.invert_output
26 bit RW FALSE hm2_7i95.0.encoder.00.sel0.is_opendrain
26 float RW 0.5 hm2_7i95.0.encoder.00.vel-timeout
26 bit RW FALSE hm2_7i95.0.encoder.01.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.01.filter
26 bit RW FALSE hm2_7i95.0.encoder.01.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.01.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.01.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.01.scale
26 float RW 0.5 hm2_7i95.0.encoder.01.vel-timeout
26 bit RW FALSE hm2_7i95.0.encoder.02.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.02.filter
26 bit RW FALSE hm2_7i95.0.encoder.02.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.02.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.02.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.02.scale
26 float RW 0.5 hm2_7i95.0.encoder.02.vel-timeout
26 bit RW FALSE hm2_7i95.0.encoder.03.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.03.filter
26 bit RW FALSE hm2_7i95.0.encoder.03.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.03.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.03.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.03.scale
26 float RW 0.5 hm2_7i95.0.encoder.03.vel-timeout
26 bit RW FALSE hm2_7i95.0.encoder.04.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.04.filter
26 bit RW FALSE hm2_7i95.0.encoder.04.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.04.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.04.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.04.scale
26 float RW 0.5 hm2_7i95.0.encoder.04.vel-timeout
26 bit RW FALSE hm2_7i95.0.encoder.05.counter-mode
26 bit RW TRUE hm2_7i95.0.encoder.05.filter
26 bit RW FALSE hm2_7i95.0.encoder.05.index-invert
26 bit RW FALSE hm2_7i95.0.encoder.05.index-mask
26 bit RW FALSE hm2_7i95.0.encoder.05.index-mask-invert
26 float RW 1 hm2_7i95.0.encoder.05.scale
26 float RW 0.5 hm2_7i95.0.encoder.05.vel-timeout
26 bit RW FALSE hm2_7i95.0.gpio.012.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.012.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.012.is_output
26 bit RW FALSE hm2_7i95.0.gpio.013.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.013.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.013.is_output
26 bit RW FALSE hm2_7i95.0.gpio.014.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.014.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.014.is_output
26 bit RW FALSE hm2_7i95.0.gpio.015.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.015.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.015.is_output
26 bit RW FALSE hm2_7i95.0.gpio.016.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.016.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.016.is_output
26 bit RW FALSE hm2_7i95.0.gpio.017.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.017.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.017.is_output
26 bit RW FALSE hm2_7i95.0.gpio.028.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.028.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.029.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.029.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.030.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.030.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.031.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.031.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.032.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.032.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.034.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.034.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.035.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.035.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.036.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.036.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.037.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.037.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.038.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.038.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.039.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.039.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.040.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.040.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.041.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.041.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.041.is_output
26 bit RW FALSE hm2_7i95.0.gpio.042.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.042.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.042.is_output
26 bit RW FALSE hm2_7i95.0.gpio.043.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.043.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.043.is_output
26 bit RW FALSE hm2_7i95.0.gpio.044.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.044.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.044.is_output
26 bit RW FALSE hm2_7i95.0.gpio.045.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.045.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.045.is_output
26 bit RW FALSE hm2_7i95.0.gpio.046.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.046.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.046.is_output
26 bit RW FALSE hm2_7i95.0.gpio.047.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.047.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.047.is_output
26 bit RW FALSE hm2_7i95.0.gpio.048.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.048.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.048.is_output
26 bit RW FALSE hm2_7i95.0.gpio.049.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.049.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.049.is_output
26 bit RW FALSE hm2_7i95.0.gpio.050.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.050.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.050.is_output
26 bit RW FALSE hm2_7i95.0.gpio.051.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.051.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.051.is_output
26 bit RW FALSE hm2_7i95.0.gpio.052.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.052.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.052.is_output
26 bit RW FALSE hm2_7i95.0.gpio.053.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.053.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.053.is_output
26 bit RW FALSE hm2_7i95.0.gpio.054.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.054.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.054.is_output
26 bit RW FALSE hm2_7i95.0.gpio.055.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.055.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.055.is_output
26 bit RW FALSE hm2_7i95.0.gpio.056.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.056.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.056.is_output
26 bit RW FALSE hm2_7i95.0.gpio.057.invert_output
26 bit RW FALSE hm2_7i95.0.gpio.057.is_opendrain
26 bit RW FALSE hm2_7i95.0.gpio.057.is_output
26 bit RW FALSE hm2_7i95.0.inmux.00.enc0_4xmode
26 bit RW FALSE hm2_7i95.0.inmux.00.enc1_4xmode
26 bit RW FALSE hm2_7i95.0.inmux.00.enc2_4xmode
26 bit RW FALSE hm2_7i95.0.inmux.00.enc3_4xmode
26 u32 RW 0x00000005 hm2_7i95.0.inmux.00.fast_scans
26 u32 RW 0x00004E20 hm2_7i95.0.inmux.00.scan_rate
26 u32 RO 0x00000018 hm2_7i95.0.inmux.00.scan_width
26 u32 RW 0x000001F4 hm2_7i95.0.inmux.00.slow_scans
26 bit RW FALSE hm2_7i95.0.io_error
26 s32 RO 1 hm2_7i95.0.packet-error-decrement
26 s32 RW 2 hm2_7i95.0.packet-error-increment
26 s32 RW 10 hm2_7i95.0.packet-error-limit
26 s32 RW 25 hm2_7i95.0.packet-read-timeout
26 s32 RW 0 hm2_7i95.0.read-request.tmax
26 bit RO FALSE hm2_7i95.0.read-request.tmax-increased
26 s32 RW 775008 hm2_7i95.0.read.tmax
26 bit RO FALSE hm2_7i95.0.read.tmax-increased
26 bit RW FALSE hm2_7i95.0.stepgen.00.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.00.direction.is_opendrain
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.00.dirhold
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.00.dirsetup
26 float RW 240 hm2_7i95.0.stepgen.00.maxaccel
26 float RW 24 hm2_7i95.0.stepgen.00.maxvel
26 float RW 10000 hm2_7i95.0.stepgen.00.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.00.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.00.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.00.step_type
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.00.steplen
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.00.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.00.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.00.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.00.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.00.table-data-3
26 bit RW FALSE hm2_7i95.0.stepgen.01.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.01.direction.is_opendrain
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.01.dirhold
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.01.dirsetup
26 float RW 240 hm2_7i95.0.stepgen.01.maxaccel
26 float RW 24 hm2_7i95.0.stepgen.01.maxvel
26 float RW 10000 hm2_7i95.0.stepgen.01.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.01.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.01.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.01.step_type
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.01.steplen
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.01.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.01.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.01.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.01.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.01.table-data-3
26 bit RW FALSE hm2_7i95.0.stepgen.02.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.02.direction.is_opendrain
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.02.dirhold
26 u32 RW 0x000007D0 hm2_7i95.0.stepgen.02.dirsetup
26 float RW 240 hm2_7i95.0.stepgen.02.maxaccel
26 float RW 24 hm2_7i95.0.stepgen.02.maxvel
26 float RW 10000 hm2_7i95.0.stepgen.02.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.02.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.02.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.02.step_type
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.02.steplen
26 u32 RW 0x000003E8 hm2_7i95.0.stepgen.02.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.02.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.02.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.02.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.02.table-data-3
26 bit RW FALSE hm2_7i95.0.stepgen.03.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.03.direction.is_opendrain
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.03.dirhold
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.03.dirsetup
26 float RW 1 hm2_7i95.0.stepgen.03.maxaccel
26 float RW 0 hm2_7i95.0.stepgen.03.maxvel
26 float RW 1 hm2_7i95.0.stepgen.03.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.03.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.03.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.03.step_type
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.03.steplen
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.03.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.03.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.03.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.03.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.03.table-data-3
26 bit RW FALSE hm2_7i95.0.stepgen.04.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.04.direction.is_opendrain
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.04.dirhold
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.04.dirsetup
26 float RW 1 hm2_7i95.0.stepgen.04.maxaccel
26 float RW 0 hm2_7i95.0.stepgen.04.maxvel
26 float RW 1 hm2_7i95.0.stepgen.04.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.04.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.04.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.04.step_type
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.04.steplen
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.04.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.04.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.04.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.04.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.04.table-data-3
26 bit RW FALSE hm2_7i95.0.stepgen.05.direction.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.05.direction.is_opendrain
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.05.dirhold
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.05.dirsetup
26 float RW 1 hm2_7i95.0.stepgen.05.maxaccel
26 float RW 0 hm2_7i95.0.stepgen.05.maxvel
26 float RW 1 hm2_7i95.0.stepgen.05.position-scale
26 bit RW FALSE hm2_7i95.0.stepgen.05.step.invert_output
26 bit RW FALSE hm2_7i95.0.stepgen.05.step.is_opendrain
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.05.step_type
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.05.steplen
26 u32 RW 0x00027FF6 hm2_7i95.0.stepgen.05.stepspace
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.05.table-data-0
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.05.table-data-1
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.05.table-data-2
26 u32 RW 0x00000000 hm2_7i95.0.stepgen.05.table-data-3
26 u32 RW 0x017D7840 hm2_7i95.0.watchdog.timeout_ns
26 s32 RW 35644 hm2_7i95.0.write.tmax
26 bit RO FALSE hm2_7i95.0.write.tmax-increased