Cannot make PWM work on MESA 7i96S

Hi,

I succesfully flash 7i96_d.bin file to Mesa 7i96S. I think I correctly configure the hafile, so I should see voltage change when I turn on PWM, on TB2 (STEP/DIR4 slot), but I cannot detect any change with Voltmeter. I turn the laser by M64 to digital pin.

No error from linuxcnc and halshow correctly shows the pwmgen.enable is true.

I measured voltage between STEP- and GND, also tried with STEP+ and GND. But no change. I set value to 1. So with Scale 1 I would expect 100percent cycle so the voltage should be 5V and 0V when disabled.

Hal file attached.

Thanks
George 

I hope you mean you flashed the 7i96s with 7i96s_d.bin...

PWM is on the spindle.

ANALOG SPINDLE INTERFACE
The 7I96S provides one analog output for spindle control. The analog output is a
isolated potentiometer replacement type device. It functions like a potentiometer with
SPINDLE+ being one end of the potentiometer, SPINDLE OUT being the wiper and
SPINDLE- being the other end. The voltage on SPINDLE OUT can be set to any voltage
between SPINDLE- and SPINDLE+. Polarity and voltage range must always be observed
for proper operation. The voltage supplied between SPINDLE+ and SPINDLE- must be
between 5VDC an 18VDC with SPINDLE + always being more positive than SPINDLE-.
Because the analog output is isolated, bipolar output is possible, for example with
SPINDLE+ connected to 5V and SPINDLE- connected to -5V, a +-5V analog output range
is created. In this case the spindle PWM must be offset so that 50% of full scale is output
when a 0V output is required. Note that if bipolar output is used, the output will be forced
to SPINDLE- at startup.
The analog output is driven by a FPGA PWM output (normally PWM 0). Optimum
PWM frequency is 10-20 KHz but frequencies from 5 KHz to 50 KHz are acceptable, lower
frequencies will have higher output ripple and higher frequencies will have worse linearity.

JT

That's correct, standard 7I96S firmware (7i96s_d.bin) has only 1 PWM generator and its
wired to the analog output on TB2.

Here is 7I96S firmware with 2 PWMGens:

 

(PWMGen 0 is wired to the analog output as usual and PWMGen 1 is wired to STEP4+/STEP4-)

Perfect thanks. I would add it to support software file on your website.

Yes, I intend to, just have not gotten to it yet...

Hi all!  I have a doubt about the analog PWM output:I ran PNCconf with mesa 7i96s in a Sherline Chucker Lathe project (I'm completely new in Linuxcnc). I could set up the axis, spindle encoder and homing tests before wire up the control box. The current step is the spindle. If I understood correctly, the Analog output (default flash) needs to be powered with a DC signal and it will behave as a pot. That is why I could not measure any signal at Analog pins when turn on the spindle?I will replace the original Sherline DC spindle motor with an AC Servo in velocity mode. In this case, how to wire the 7i96s Analog output to the servo drive (pins 26 and 11)?

image missing https://forum.linuxcnc.org/media/kunena/attachments/34018/CapturadeTela2023-02-03as14.01.15.png

]JT post=263438 userid=32471I hope you mean you flashed the 7i96s with 7i96s_d.bin...PWM is on the spindle.

ANALOG SPINDLE INTERFACEThe 7I96S provides one analog output for spindle control. The analog output is aisolated potentiometer replacement type device. It functions like a potentiometer withSPINDLE being one end of the potentiometer, SPINDLE OUT being the wiper andSPINDLE- being the other end. The voltage on SPINDLE OUT can be set to any voltagebetween SPINDLE- and SPINDLE . Polarity and voltage range must always be observedfor proper operation. The voltage supplied between SPINDLE and SPINDLE- must bebetween 5VDC an 18VDC with SPINDLE always being more positive than SPINDLE-.Because the analog output is isolated, bipolar output is possible, for example withSPINDLE connected to 5V and SPINDLE- connected to -5V, a -5V analog output rangeis created. In this case the spindle PWM must be offset so that 50% of full scale is outputwhen a 0V output is required. Note that if bipolar output is used, the output will be forcedto SPINDLE- at startup.The analog output is driven by a FPGA PWM output (normally PWM 0). OptimumPWM frequency is 10-20 KHz but frequencies from 5 KHz to 50 KHz are acceptable, lowerfrequencies will have higher output ripple and higher frequencies will have worse linearity.JT