Update: PREOP reached, full SII EEPROM interface workingQuick update on the Colorlight 5A-75E EtherCAT slave.Since my last post, quite a bit has moved:
What works now:
- SII EEPROM emulation fully implemented and verified with IgH master
-
reads identity correctly:
- Vendor Id:
, Product code:
- All SII categories parsed: STRINGS, GENERAL, FMMU, SYNCM
- AL state machine:
- IgH configures SM0/SM1 and accepts the slave in PREOP
Current limitation:
CoE mailbox is not implemented on the FPGA side yet, so IgH fails on
CoE SDO upload (
PDO assign) and never reaches SAFEOP/OP.
Next steps:
- Remove CoE declaration from ESI to bypass mailbox requirement for
Phase 1 (bring-up with LinuxCNC and quadrature encoders)
- Then decide: implement mailbox via VexRiscv + SOES (Phase 2), or
keep CoE-free with PDO mapping from ESI
Repository:
github.com/romanetz/liteethercat
Architecture and roadmap:
Code:
docs/architecture.md
in the repo.The project continues the same modular LiteX approach. Once the slave
is in OP and HAL pins react to encoder movement, I'll post a video.