My notes on compiling LiteX-CNC on linuxCNC

I've restored my virtual machine again, so it's a fresh install of linuxcnc. Now it works when I specifically run python3

$ sudo apt-get install wget
$ sudo apt-get install python3-pip
$ sudo apt-get install git
$ pip3 install --user meson ninja

$ mkdir LiteX
$ cd LiteX
$ wget raw.githubusercontent.com/enjoy-digital/...aster/litex_setup.py
$ python3 litex_setup.py --init --install --config=standard --gcc=riscv
$ cd ..

$ wget github.com/YosysHQ/oss-cad-suite-build/r...nux-x64-20220920.tgz
$ tar -xvf oss-cad-suite-linux-x64-20220920.tgz
$ mkdir -p ~/bin
$ ln -s ~/oss-cad-suite/bin/* ~/bin/
#start a new bash, so ~/bin is added to the PATH
$ bash --login

$ git clone github.com/Peter-van-Tol/LiteX-CNC.git
$ cd LiteX-CNC
$ git checkout stepgen_improvement
$ pip3 install -r requirements.txt

$ python3 -m firmware examples/5a-75e.json
<module 'firmware' from '/home/cedric/LiteX-CNC/firmware/__init__.py'>
Generated fingerprint (CRC):  2614875155
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:

---

INFO:SoC:Creating SoC... (2022-09-28 01:26:07)
INFO:SoC:

---

INFO:SoC:FPGA device : LFE5U-25F-6BG256C.
INFO:SoC:System clock: 50.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:

---

INFO:SoC:Initial SoC:
INFO:SoC:

---

INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:

---

INFO:SoC:Controller ctrl added.
INFO:SoC:CPU None added.
INFO:SoC:CPU None adding IO Region 0 at 0x00000000 (Size: 0x100000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys of 50.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 sys_ps of 50.00MHz (+-10000.00ppm).
INFO:SoCBusHandler:master0 added as Bus Master.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectPointToPoint (1 <-> 1).
INFO:SoCCSRHandler:MMIO_inst CSR allocated at Location 0.
INFO:SoCCSRHandler:ctrl CSR allocated at Location 1.
INFO:SoCCSRHandler:ethphy CSR allocated at Location 2.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 3.
INFO:SoC:

---

INFO:SoC:Finalized SoC:
INFO:SoC:

---

INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False
Bus Regions: (1)
csr                 : Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (1)
- master0
Bus Slaves: (1)
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- MMIO_inst      : 0
- ctrl           : 1
- ethphy         : 2
- identifier_mem : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:

---

INFO:ECP5PLL:Config:
clki_div   : 1
clkfb      : 2
clko0_freq : 50.00MHz
clko0_div  : 8
clko0_phase: 0.00°
clko1_freq : 50.00MHz
clko1_div  : 8
clko1_phase: 180.00°
clko2_div  : 1
vco        : 400.00MHz
clkfb_div  : 16
cedric@mill:~/LiteX-CNC$

The generated files are in 5a-75e:
$ cd 5a-75e/
$ find
./software
./software/include
./software/include/generated
./software/include/generated/soc.h
./software/include/generated/mem.h
./software/include/generated/git.h
./software/include/generated/csr.h
./gateware
./gateware/colorlight_5a_75e.lpf
./gateware/colorlight_5a_75e.ys
./gateware/colorlight_5a_75e_mem.init
./gateware/build_colorlight_5a_75e.sh
./gateware/colorlight_5a_75e.v
./csr.csv

The .lpf file can be flashed into the FPGA


 

This is the same procedure on arch linux:

# pacman -S wget
# pacman -S python-pip
# pacman -S git
$ pip3 install --user meson ninja

$ mkdir LiteX
$ cd LiteX
$ wget raw.githubusercontent.com/enjoy-digital/...aster/litex_setup.py
$ python3 litex_setup.py --init --install --config=standard --gcc=riscv
$ cd ..

$ wget github.com/YosysHQ/oss-cad-suite-build/r...nux-x64-20220920.tgz
$ tar -xvf oss-cad-suite-linux-x64-20220920.tgz
$ mkdir -p ~/bin
$ ln -s ~/oss-cad-suite/bin/* ~/bin/
$ bash --login

$ git clone github.com/Peter-van-Tol/LiteX-CNC.git
$ cd LiteX-CNC
$ git checkout stepgen_improvement
$ pip3 install -r requirements.txt
$ python3 -m firmware examples/5a-75e.json

The commands above do generate the verilog code, but not the bitstream. In the directory 5a-75e there's the script build_colorlight_5a_75e.sh:
$ cat build_colorlight_5a_75e.sh
# Autogenerated by LiteX / git: ac369977
set -e
yosys -l colorlight_5a_75e.rpt colorlight_5a_75e.ys
nextpnr-ecp5 --json colorlight_5a_75e.json --lpf colorlight_5a_75e.lpf --textcfg colorlight_5a_75e.config --25k --package CABGA256 --speed 6 --timing-allow-fail --seed 1
ecppack --bootaddr 0 --compress colorlight_5a_75e.config --svf colorlight_5a_75e.svf --bit colorlight_5a_75e.bit

as the paths on my machine are not setup correctly, I had to adjust this script to include the full locations:
$ cat my_build_colorlight_5a_75e.sh
# Autogenerated by LiteX / git: ac369977
set -e
/home/cedric/oss-cad-suite/bin/yosys -l colorlight_5a_75e.rpt colorlight_5a_75e.ys
~/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_5a_75e.json --lpf colorlight_5a_75e.lpf --textcfg colorlight_5a_75e.config --25k --package CABGA256 --speed 6 --timing-allow-fail --seed 1
~/oss-cad-suite/bin/ecppack --bootaddr 0 --compress colorlight_5a_75e.config --svf colorlight_5a_75e.svf --bit colorlight_5a_75e.bit

Now the script runs correctly:
$ sh my_build_colorlight_5a_75e.sh

/

---

\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\

---

/

Yosys 0.21+10 (git sha1 a21745052, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Executing script file `colorlight_5a_75e.ys' --

1. Executing Verilog-2005 frontend: /home/cedric/LiteX-CNC/5a-75e/gateware/colorlight_5a_75e.v
Parsing Verilog input from `/home/cedric/LiteX-CNC/5a-75e/gateware/colorlight_5a_75e.v' to AST representation.
Storing AST representation for module `$abstract\colorlight_5a_75e'.
Successfully finished Verilog frontend.

2. Executing ATTRMAP pass (move or copy attributes).

3. Executing SYNTH_ECP5 pass.
<snip>
Warning: Max frequency for clock '$glbnet$crg_clkout0': 42.39 MHz (FAIL at 50.00 MHz)
Warning: Max frequency for clock '$glbnet$eth_clocks_rx$TRELLIS_IO_IN': 112.17 MHz (FAIL at 125.00 MHz)

Info: Max delay <async> -> posedge $glbnet$crg_clkout0 : 2.90 ns
Info: Max delay posedge $glbnet$crg_clkout0 -> <async> : 5.18 ns
Info: Max delay posedge $glbnet$crg_clkout0 -> posedge $glbnet$eth_clocks_rx$TRELLIS_IO_IN: 2.22 ns
Info: Max delay posedge $glbnet$eth_clocks_rx$TRELLIS_IO_IN -> posedge $glbnet$crg_clkout0 : 1.84 ns

Info: Slack histogram:
Info: legend: * represents 47 endpoint(s)
Info: + represents [1,47) endpoint(s)
Info: [ -3591, 649) |****+
Info: [ 649, 4889) |*****************+
Info: [ 4889, 9129) |****************************************************+
Info: [ 9129, 13369) |************************************+
Info: [ 13369, 17609) |************************************************************
Info: [ 17609, 21849) |******************************************+
Info: [ 21849, 26089) |
Info: [ 26089, 30329) |
Info: [ 30329, 34569) |
Info: [ 34569, 38809) |
Info: [ 38809, 43049) |
Info: [ 43049, 47289) |
Info: [ 47289, 51529) |
Info: [ 51529, 55769) |
Info: [ 55769, 60009) |
Info: [ 60009, 64249) |
Info: [ 64249, 68489) |
Info: [ 68489, 72729) |
Info: [ 72729, 76969) |
Info: [ 76969, 81209) |+
2 warnings, 0 errors

Info: Program finished normally.

now the gateware directory has a lot more files:
$ ls -l
total 17716
-rw-r--r-- 1 cedric cedric 389 Oct 8 17:22 build_colorlight_5a_75e.sh
-rw-r--r-- 1 cedric cedric 214083 Oct 12 20:47 colorlight_5a_75e.bit
-rw-r--r-- 1 cedric cedric 3211208 Oct 12 20:47 colorlight_5a_75e.config
-rw-r--r-- 1 cedric cedric 10343649 Oct 12 20:46 colorlight_5a_75e.json
-rw-r--r-- 1 cedric cedric 3459 Oct 8 17:22 colorlight_5a_75e.lpf
-rw-r--r-- 1 cedric cedric 105 Oct 12 20:23 colorlight_5a_75e_mem.init
-rw-r--r-- 1 cedric cedric 2698676 Oct 12 20:46 colorlight_5a_75e.rpt
-rw-r--r-- 1 cedric cedric 453587 Oct 12 20:47 colorlight_5a_75e.svf
-rw-r--r-- 1 cedric cedric 1188497 Oct 12 20:23 colorlight_5a_75e.v
-rw-r--r-- 1 cedric cedric 303 Oct 8 17:22 colorlight_5a_75e.ys
-rw-r--r-- 1 cedric cedric 461 Oct 12 20:46 my_build_colorlight_5a_75e.sh

The file "colorlight_5a_75e.svf" can now be flashed into the FPGA board