The limitation is at 96 I/O maximum it could be very low for some specific applications, maybe we could find a way to reach 128 or 256 user I/O using some new FPGA like ARTIX 35K or 100K, or creating 2x HM2 firmware in a single FPGA if there is enough cells. it could be very easy and with a double SPI communication (SPI0 and SPI1) 2x96 = 192 I/O
Current IDROM format limits I/O to 144 pins not 96, raising this to 1024 or so would really only mean increasing the IDROM size and changing a few constants. This is independent of FPGA type.
