Mesa 7i39+5i20
- BigJohnT
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John
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- nikos.chalikias
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Motor: Nanotec NEMA23 BLDC with Hall sensors
Attached encoder AVAGO HEDS-5540 with 1000 pulses/rot and Index
Sinusiodal commutation is preffered as the torque is smoother.
Initialisation phase with half turn movement seems acceptable.
Is it really BLAC driving with bldc_sinus driver?
I guess you are using 7i43 AnyI/O card.
I use 5i20. Is it OK to replace text [7i43] with text [5i20] in the .hal file?
Should I take care of .PIN files?
Is the pinout of 5i20 asigned automatically?
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- andypugh
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hm2_7i43 to hm2_pci in the "loadrt" line.
Elsewhere it will be just a case of swapping 7i43 for 5i20.
Start emc from the command line and see what happens with no motors connected.
dmesg will be useful, it tells you the pin assignments on the 5i20 card.
However, the pinout is designed to let you plug a 50-way header directly between the 5i20 and one or more 7i39s so the pinout is the same on any board, and only matters if you want to break-out unused pins for GPIO. (which you should be able to do with a second connector on the same ribbon cable)
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- nikos.chalikias
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dmesg output is here

Probably is default driver for hm2_pci
First PWM OUT should be to PINS 19,43 of P2 connector, using different names.
5i20.ini and bldc_sine.hal seem correct (..to me) and they are in the right place. ...attached in next 2 messages
I can not find where SVST8_4.BIT and svtp4_7i39.bit are located. I guess they are to root somewhere...
Can you understand what is wrong?
[ 2397.847996] hm2: loading Mesa HostMot2 driver version 0.15
[ 2397.851143] hm2_pci: loading Mesa AnyIO HostMot2 driver version 0.6
[ 2397.851181] hm2_pci: discovered 5i20 at 0000:03:02.0
[ 2397.851313] hm2_5i20.0: firmware: requesting hm2/5i20/SVST8_4.BIT
[ 2397.994706] hm2/hm2_5i20.0: 72 I/O Pins used:
.....
[ 2397.994738] hm2/hm2_5i20.0: IO Pin 006 (P2-13): PWMGen #1, pin Out0 (PWM or Up) (Output)
[ 2397.994742] hm2/hm2_5i20.0: IO Pin 007 (P2-15): PWMGen #0, pin Out0 (PWM or Up) (Output)
[ 2397.994746] hm2/hm2_5i20.0: IO Pin 008 (P2-17): PWMGen #1, pin Out1 (Dir or Down) (Output)
[ 2397.994750] hm2/hm2_5i20.0: IO Pin 009 (P2-19): PWMGen #0, pin Out1 (Dir
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- nikos.chalikias
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- andypugh
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Settings only get transferred from INI to HAL by use of the [STANZA](setting) format. There is no other linkage between them other than that EMC2 reads the INI file to get the names of the HAL files it needs to run at startup.
b]nikos.chalikias wrote:[/b]
I don't think there is a default firmware, but I could be wrong.Probably is default driver for hm2_pci
It does seem that the wrong .BIT file is being loaded into the driver. This is the reason that the pin names (and functions) on the connector are wrong.First PWM OUT should be to PINS 19,43 of P2 connector, using different names.
5i20.ini and bldc_sine.hal seem correct (..to me) and they are in the right place. ...attached in next 2 messages
I can not find where SVST8_4.BIT and svtp4_7i39.bit are located. I guess they are to root somewhere...
You can see what actual BIT files you have available in /lib/firmware/hm2/
You need to choose one which is in the lib/firmware/5i20 directory and has a name which includes "tp", possibly tpen6_6.pin
My hal files were set up to use experimental bit files. I don't know what files (if any) are in the current firmware collection.
You might need to get a firmware update (sudo apt-get update hostmot2-firmware ) or direct download from emergent.unpy.net/01267622561
I do notice that the hal file name specified in your INI file is not the same as the name of the file you have posted. Those definitely need to match.
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- nikos.chalikias
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Is this a BLDC driver?
Should I used it instead svtp4_7i39.bit
is it sinus or hall commutation?
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- andypugh
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You should definitely use it instead of svtp4_7i49.bit as I think that svtp4_7i30.bit only exists on about 2 hard-drives in the world, and yours is not one of them.
The distinction between Hall and Sinusoidal commutation depends only on the HAL component used (bld3_hall3 or bldc_sine). The Hostmot2 driver simply takes 3 three-phase amplitudes and converts them to phase-locked PWM values on the connector pins.
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- nikos.chalikias
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from dmseg output
seems that 5i20 is configured to drive BLDC driver-card.
but
pin-out does not match to 7i39!
It needs an extra interface board, just to match the 5i20-7i39 pins

all pwm signals are to P2 , all encoders to P4.
I found that TPEN6_6.XML controls the pin-out.
I could edit this file and place the pins in the right places. Is this OK to do?
Are there any rules to follow in the editing of this XML?
but
Why are the pins put in this order? Is there a good reason? The person who made all this development, must had something in mind!
What was that?
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