Mesa StepGen ouputs with Yaskawa servos

More
4 years 11 months ago #226876 by johnbl
So I've been finally able to connect my Yaskawa servos to my 7i85s but I'm getting mixed results: it seems like the pulse train is not reliable and sometimes the servo drive does not recognize the pulses.

After taking a closer look at the 7i85s and assuming I can read correctly the datasheet of the ISL32174E used as differential driver, the diff. output voltage is not 5V but more like 4V. Not a huge issue, with a 120R series resistor there should still be about 10mA flowing through the opto-LED.

However I also noticed that the step/dir outputs from the fpga are terminated with a Thevenin termination (220R pullup to 3.3V and 470R pulldown to ground), which brings the voltage down to about 2.3V.
As per the ISL3217 datasheet, this is below the minimum 2.7V required for a logic HIGH.
Could this be the issue or am I wide of the mark?

Please Log in or Create an account to join the conversation.

More
4 years 11 months ago #226879 by PCW
The open circuit voltage of the terminator will be close to 2.3V but driven high ,
it will be closer to 2.7 or 2.8V (and about .4V when driven low) I don't think this is an
issue. What step length are you using? I would always start with at least 2X the drives
minimum step length value.
 

Please Log in or Create an account to join the conversation.

More
4 years 11 months ago #226880 by johnbl
Right, I can indeed measure about 2.8V. Still, this seems way too close to the minimum threshold.

I'm currently using 1us wide pulses for steps and 5us for dir, which is well within spec:
 

Please Log in or Create an account to join the conversation.

More
4 years 11 months ago - 4 years 11 months ago #226884 by PCW
2.8V is a legal high (the actual input thresholds are about 1.7V)
Its also about the best you can do into termination with 3.3V drive.

Note that the minimum VIH and VIL specifications are not the
input threshold values but the minimum high and low levels to
guarantee sufficient noise margin (typically 1.0V for TTL interface
levels like these)

As an experiment, you can get a bit higher drive by setting the
FPGA card I/O to 3.3V tolerant mode which reduces the output
resistance, but this is not the issue, its something else.
Last edit: 4 years 11 months ago by PCW.
The following user(s) said Thank You: johnbl

Please Log in or Create an account to join the conversation.

More
4 years 11 months ago #226889 by johnbl
Thanks for the explanation.
I'll keep investigating and probing.

Please Log in or Create an account to join the conversation.

More
2 years 10 months ago #288257 by LeikaSadDog
Hi

I am planning to use Yaskawa sgd7s with a mesa 7176e. Did you find a solution for the lost steps? Best jannik, Switzerland

Please Log in or Create an account to join the conversation.

Moderators: PCW, jmelson
Time to create page: 0.321 seconds
Powered by Kunena Forum