7i92 custom Bit File- which ISE Version to use?

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26 Dec 2020 11:42 #193218 by FedX
Hi,

i`m trying to create a custom bit file for my mesa 7i92. I used a virtual win7 machine and ISE v14.5. When i try to open the project "seveni92.xise" it tells me that this project is created with an older version, but which one ?!

I migrated the project and except that it can't find some files it first seems to work. But when i modify TopEthernetHostMot2 it tells me that there is a syntax failure near "entity":
-- dont change anything below unless you know what you are doing -----
	
entity TopEthernetHostMot2 is -- for 7I80DB,7I80HD,7I77E,7I76E,7I92,7I93,7I96,7I97
	 generic 
	 (
		ThePinDesc: PinDescType := PinDesc;
		TheModuleID: ModuleIDType := ModuleID;
		PWMRefWidth: integer := 13;	-- PWM resolution is PWMRefWidth-1 bits 
		IDROMType: integer := 3;		
		UseStepGenPrescaler : boolean := true;
		UseIRQLogic: boolean := true;
		UseWatchDog: boolean := true;
		OffsetToModules: integer := 64;
		OffsetToPinDesc: integer := 448;
		BusWidth: integer := 32;
		AddrWidth: integer := 16;
		InstStride0: integer := 4;			-- instance stride 0 = 4 bytes = 1 x 32 bit
		InstStride1: integer := 64;		-- instance stride 1 = 64 bytes = 16 x 32 bit registers sserial
--		InstStride1: integer := 16;		-- 4..7 16 for BSPI/UART Ick double Ick
		RegStride0: integer := 256;		-- register stride 0 = 256 bytes = 64 x 32 bit registers
		RegStride1: integer := 256;      -- register stride 1 = 256 bytes - 64 x 32 bit
		FallBack: boolean := false			-- is this a fallback config?

		);

Whats the problem here?

And i've seen that many PIN Files have this line:
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),

do i need this line what is it doing?

best regards
Dominik

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26 Dec 2020 15:49 - 26 Dec 2020 15:53 #193237 by PCW
1. Any ISE version from 13.1 to 14.7 will work
2. The error is probably due to a syntax error above in the card and pinfile selection areas
3. The DPLL is used to retime critical operations (such as reading encoder and stepgen
positions) and pre-trigger some operations (like absolute encoder start of transfer)
It is suggested for Ethernet connected devices as they tend to have higher access jitter
The DPLL can reduce the timing uncertainty from 100s of usec to less than 300 ns
Last edit: 26 Dec 2020 15:53 by PCW.
The following user(s) said Thank You: tommylight, FedX

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27 Dec 2020 16:07 #193299 by FedX
Hi,

it finally worked with V14.7 thank you for explaining the DPLL. Is there a dosumentation were i can find all the functions?

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27 Dec 2020 17:31 #193303 by PCW
It will work with any version between 13.1 and 14.7
(The distributed project files are from 13.1, the last version that working
block copy in the editor)

The DPLL pins are described in the hostmot2 manual page
The following user(s) said Thank You: FedX

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