RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error

Hello,

I have adopted the initial pin configuration for to prepare the bitstream for RV901T:  github.com/golyakoff/hostmot2-rv901t-7i9...5ec35/PIN_AGO_72.vhd . 
this works fine until I try to set the number of PMW to at least 1.

I.e. this is implementing fine:
but anyway this bitstream doesn't allow to start linuxcnc:
Probably it shouldn't start as there are no PMW but it is declared... I'm not sure, anyway the goal is to have at least 1 PMV Generator. But when I change the number to x"01"...
...the error appears on the Mapping phase:
Here is the error message:

Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site <M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>. Each BUFIO site has a select set of IOBs that can drive it. If these IOBs are not used, the connection is not routable You may want to analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
< NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; >

I see that Xilinx ISE tries to say me something with these words: "The clock IOB component <CLK> is placed at site <M9>... " but I don't know it well, honestly.

I tried to decrease the number of StepGens and QCounts, I even started with just 71 general I/O pins with the only "PWMAOutPin" but it doesn't work anyway. From this I make a conclusion from that the problem doesn't related to the free part of crystal but more related to the constraints.

What I understand (correct me if I wrong) all other modules are working on 100 MHz frequency, but PWM is working on 200 MHz, it is my "CLK" net and it somehow should be available to the the PWM but it doesn't.

I will appreciate for the possible suggestions.

I think the issue is a "banking issue".

I'd try moving the PWM pin to a pin on the same bank as the clk pin.

I had this issue when first working with SPI.

The attached file has the Pin Locations to banks.

This is just a guess based on the issues I had when first working with SPI on a dev board, but I haven't seen it when building with PWM.

Pete will have the right fix for sure.

I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...

Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not
placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site
<M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>

This looks to me to possibly be a .ucf file pinout error (an actual clock input is not placed at a
physical GCLK pin)

This could be the main clock or the SPI clock input on the host interface (it may also be an
error in the clock multiplier setup)

tommylight wrote:

I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...

Maybe "Driver Boards" would be the most appropriate section, as thta is what we are discussing. And the OP orignal thread as well.

Honestly I not too sure why another topic was need, it's all to do with getting hostmot2 firmware going on another board.

PCW wrote:

Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not
placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site
<M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>

This looks to me to possibly be a .ucf file pinout error (an actual clock input is not placed at a
physical GCLK pin)

This could be the main clock or the SPI clock input on the host interface (it may also be an
error in the clock multiplier setup)

The clock in on this pin.
M9 2 BR IO_L29P_GCLK3_2

I can confirm it works, twas fine when meddling with the Smart Serial stuff.

I got that message, similar anyways, when I was trying to get the SPI firmware going. After some digging, trying to understand the Xlilinx data sheets, I came to the conclusion that I need the SPI_COMM pins in the same bank as the clk on the dev board I was using. I can't say I saw the same issue with PWM but maybe I was just lucky with my choice of pins.