7I90HD via LBP16/RS-422 for custom Java application (not LinuxCNC) — need mesafl

Hello Mesa community and PCW,

I am using a Mesa 7I90HD card in a non-LinuxCNC application. My system 
is a custom Java-based front panel application running on a Windows 11 
laptop that communicates to six independent DSP boards via the 7I90HD 
acting as an intelligent I/O interface. I am NOT using LinuxCNC — I am 
implementing the LBP16 protocol directly in Java over a USB-to-RS422 
serial connection to the 7I90HD's J1 RJ-45 connector.

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SYSTEM OVERVIEW
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  Windows 11 Laptop (Java LBP16 application)
      ↓  USB port
  USB-to-RS422 converter (FTDI-based)
      ↓  RS-422 to J1 on 7I90HD (115200 baud, LBP16)
  Mesa 7I90HD (Spartan-6 FPGA, HostMot2 firmware)
      ↓  P1 connector (24 signals), P2, P3 Connectors
  6 × DSP boards (I1, I2, I3, V1, V2, V3)

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SIGNAL REQUIREMENTS (24 pins total on P1)
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Per DSP board (6 boards × 4 signals = 24 pins):
  • UART TX  → DSP SCI RX  (Java sends ASCII setpoints e.g. "1.0", "110")
  • UART RX  ← DSP SCI TX  (DSP sends status/ack back to Java)
  • GPIO OUT → DSP Enable/Disable command
  • GPIO IN  ← DSP Over-Temperature flag (contact closure = HIGH)

All DSP boards use optocoupler isolation between their circuitry 
and the 7I90HD I/O pins.

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QUESTION 1 — mesaflash.exe for Windows 11
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The 7I90HD manual (v1.7, page 19) states: "Linux and Windows utility 
programs mesaflash and mesaflash.exe are provided to write configuration 
files to the 7I90HD EEPROM via the RS-422 interface and LBP16."

My supplied 7i90.zip package contains:
  7i90\utils\linux\  → mesaflash  and  mesaflash3  (Linux binaries)
  7i90\utils\dos\    → nmflash, READHMID, RP32, WP32, enve (DOS tools)

I cannot find mesaflash.exe for Windows anywhere in this package.
The LinuxCNC GitHub (LinuxCNC/mesaflash/releases) does not provide 
pre-built Windows binaries.

QUESTION: Please advise — 
  a) Is mesaflash.exe available from Mesa directly? If so, where?
  b) Can mesaflash be compiled with MSYS2/MinGW-w64 on Windows 11 
     for serial/LBP16 use? Are there any known issues or patches needed?
  c) Is the Ubuntu Live USB approach (boot Linux temporarily, run 
     the supplied mesaflash binary, reboot to Windows) a supported 
     and safe method to flash the 7I90HD?

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QUESTION 2 — Correct bitfile for my application
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From my supplied bitfiles I have identified:
  • 7i90_Serial_svua8_4.bit  — 4 UART instances (insufficient for 6 boards)
  • 7i90_Serial_svua8_8.bit  — 8 UART instances (covers all 6 boards)

I also received direct confirmation from Mesa tech support that 
"hm2-serial or sserial modes" are appropriate for RS-422 use.

QUESTION: Please confirm —
  a) Is 7i90_Serial_svua8_8.bit the correct bitfile for 6 independent 
     UART TX/RX channels plus GPIO, accessed via LBP16 from a custom 
     host application (no LinuxCNC)?
  b) Are all 8 UART instances in this bitfile standard async UART 
     (compatible with plain SCI on a TI DSP at configurable baud rate), 
     or are they Mesa Smart Serial (sserial) protocol only?

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QUESTION 3 — PIN file for svua8_8
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My supplied 7i90.zip does NOT include a .pin file for 
7i90_Serial_svua8_8.bit. The .pin file is essential because I need 
to know the exact IO pin numbers for:
  • UART0_TX through UART5_TX  (6 output pins → DSP SCI RX)
  • UART0_RX through UART5_RX  (6 input pins  ← DSP SCI TX)
  • Remaining GPIO available    (for 6 Enable outputs + 6 Temp inputs)

My Java LBP16 driver uses these pin numbers to set the correct bits 
in the DDR register (0x1100), ALT-SRC register (0x1200), and GPIO 
data register (0x1000) in HostMot2 Space 0.

QUESTION: Could anyone supply the .pin file for 
7i90_Serial_svua8_8.bit, or post its UART and GPIO pin assignments?

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QUESTION 4 — HostMot2 UART module register layout
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My Java driver reads the IDROM at Space 0 address 0x0400 to discover 
each UART module's base address (via GTag identification). I then need 
to access the UART TX FIFO, RX FIFO, and baud rate registers at offsets 
from that base address.

The 7I90HD manual covers GPIO register layout but does not document 
the HostMot2 UART module register offsets. The regmap file in the 
HostMot2 VHDL source should have this, but I cannot easily access it 
from Windows.

QUESTION: Can anyone confirm or share the HostMot2 UART module 
register map? Specifically:
  • Offset from module base for TX data FIFO write register
  • Offset from module base for RX data FIFO read register
  • Offset from module base for baud rate divisor register
  • Baud rate divisor formula for 50 MHz FPGA clock

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ADDITIONAL CONTEXT
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- I have already received helpful technical guidance from Mesa support 
  confirming GPIO register addresses (0x1000, 0x1100, 0x1200 etc.) 
  and the recommendation to use hm2-serial mode for RS-422 links.

- My Java LBP16 driver handles:
  - LBP16 command word encoding (W/A/C/M/S/I/N bit packing)
  - IDROM parsing (Space 0, 0x0400) to discover module addresses
  - GPIO DDR and ALT-SRC configuration at startup
  - Batched GPIO poll + uSTimeStampReg read in a single LBP16 packet
    for precise START/STOP timing measurement

- The 7I90HD is not running as a LinuxCNC slave — it is a standalone  
  LBP16 register-accessible FPGA I/O interface for a custom industrial 
  measurement application. The DSP boards convert received ASCII 
  setpoints (e.g. "1.0A", "110V") into sinusoidal waveforms via their 
  internal DAC for driving power amplifiers.

Thank you very much for any assistance. This forum and the Mesa 
community have been invaluable resources.