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- 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
- Gotrune
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23 Sep 2026 18:03 #349814
by Gotrune
7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors) was created by Gotrune
Hi PCW,I am currently retrofitting a machine with a Mesa 7i97T and JAT Ecovario drives controlling permanent magnet linear motors.My problem is that my high-resolution optical scales (1µm/step which are passed-through directly from the drives, with no hardware division possible) are dropping pulses during high acceleration, even with "filter 0" set in my HAL file. The minimum edge separation of the raw encoder signals is too tight and violates the standard MuxedQCount clock limit.Could you please compile a custom bitfile for the 7i97T where the encoder counting module clock is bumped to 200MHz (or the maximum possible frequency for this FPGA) to handle these extremely fast edges?I only need the standard 7i97T I/O pinout, just with the fastest possible encoder sampling.Thank you in advance!Please Log in or Create an account to join the conversation.
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23 Sep 2026 18:29 #349815
by PCW
Replied by PCW on topic 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
I would try setting:
hm2_7i97.0.encoder.muxed-sample-frequency
to say 20 MHz
(you can probably go higher by futzing with the muxed- skew parameter)
hm2_7i97.0.encoder.muxed-sample-frequency
to say 20 MHz
(you can probably go higher by futzing with the muxed- skew parameter)
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23 Sep 2026 19:16 #349816
by Gotrune
Replied by Gotrune on topic 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
Hi PCW,
Thank you so much for the incredibly fast reply!
I will add setp hm2_7i97.0.encoder.muxed-sample-frequency 20000000 to my HAL file right away and test the machine.
Just to make sure I fully understand the limits of the hardware: what are the acceptable or maximum values for this parameter with the standard 7i97T bitfile? For example, does it need to be a specific integer divisor of the base clock? Also, at what frequency would I typically need to start adjusting the muxed-skew parameter you mentioned?
Thanks again for your time and excellent support!
Thank you so much for the incredibly fast reply!
I will add setp hm2_7i97.0.encoder.muxed-sample-frequency 20000000 to my HAL file right away and test the machine.
Just to make sure I fully understand the limits of the hardware: what are the acceptable or maximum values for this parameter with the standard 7i97T bitfile? For example, does it need to be a specific integer divisor of the base clock? Also, at what frequency would I typically need to start adjusting the muxed-skew parameter you mentioned?
Thanks again for your time and excellent support!
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- tuxcnc
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23 Sep 2026 19:33 #349817
by tuxcnc
Only maximum speed matters.
From the resolution and speed you will calculate the pulse frequency.
Replied by tuxcnc on topic 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
Acceleration has nothing to do with it.
[/code][/code][code][code]my high-resolution optical scales (...) are dropping pulses during high acceleration
Only maximum speed matters.
From the resolution and speed you will calculate the pulse frequency.
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23 Sep 2026 19:49 #349818
by Gotrune
Replied by Gotrune on topic 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
Oh, yes I understand,
Thx
Thx
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23 Sep 2026 21:21 #349824
by PCW
Replied by PCW on topic 7i97T - Custom bitfile request (High-speed 200MHz Encoder for Linear Motors)
20 or 25 MHz (2.4x or 3x faster than the default 8.3333 MHz), works fine with no skew added.
I would be comfortable with those settings.
The frequency value you set will be rounded to the closest available frequency
= an integer division of the 100 Mhz FPGA ClockLow. This is easy to test with halshow.
As you go faster, the timing margins become smaller and you must adjust to the delay in
the actual hardware multiplexing with the skew adjust (in ns) but at the higher speeds
the timing variations over voltage and temperature limit the practical maximum.
That is, I can get all encoders to work with a 50 MHz mux rate (and 20 ns skew) but I would not trust
it without doing at least a temperature cycle.
Timing errors will show up as even/odd encoder swaps or crossover between even/odd encoders
so don't experiment on a powered servo system...
I would be comfortable with those settings.
The frequency value you set will be rounded to the closest available frequency
= an integer division of the 100 Mhz FPGA ClockLow. This is easy to test with halshow.
As you go faster, the timing margins become smaller and you must adjust to the delay in
the actual hardware multiplexing with the skew adjust (in ns) but at the higher speeds
the timing variations over voltage and temperature limit the practical maximum.
That is, I can get all encoders to work with a 50 MHz mux rate (and 20 ns skew) but I would not trust
it without doing at least a temperature cycle.
Timing errors will show up as even/odd encoder swaps or crossover between even/odd encoders
so don't experiment on a powered servo system...
The following user(s) said Thank You: tommylight
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