Systematic approach to tracking down latency issue

PCW,

Just trying to understand this a bit better.

Related, but not the same I think.Would a 7i77 or similar outputting +/-10v be outputting a consistent voltage per base servo thread update? Or will it alter voltage depending on encoder count/rate?

I'm guessing it's the former?

Slightly related second question. So if I had a machine moving at 16.66ips(1000ipm) that hit a hard stop and had an f-error configured of anything less than 0.0166, assuming average timings of hard stop impact vs where in the servo thread we are, it'd be reasonable to say that the f-error trip wouldn't happen for 2 servo thread cycles? The first cycle would see some F-error and start accelerating the machine, and the second cycle would find that F-error has been exceeded and disable drives/power off.

Thanks to everyone who has contributed to this topic.

It wasn't clear to me when I set up my machine that the parallel port was such a potentially risky piece of hardware. It did seem like a nice free ride though

From what I understand from PCW the odd latency on 1ms might be acceptable depending on the acceleration of a machine. My machine's acceleration is more like 1/12G.

PCW, can you comment of the appropriate HAL plumbing to minimise these issues?

Time for me to buy a MESA board