Load FIFO code into 6125 FPGA with PCIE connection

Hello everyone,

I am learning about FPGA, and I would like to know how can I link my 6125 Superport FPGA based PCIE Anything I/O Card, Spartan 6 in order to load the code from this website: www.deathbylogic.com/2013/07/vhdl-standard-fifo/

The main idea is to make a FIFO but I would like to know how the pin assignment is done ? I have a UCF file but I don't know how can I change the value of one LED in the testbench to make it blink or at least to light it on.

Since the card doesn't use a USB cable but a PCIE connection, is ISE Design Suite 14.7 (WebPACK edition) a good soft to load my code into the FPGA with iMPACT ?

I already did light on the LEDS USER0 and USER1 with some lines of code on the terminal. But now I need to make a FIFO with a file that I would load into the FPGA.

Can you give me some advices or answers to my problems please?

Thanks in advance for replying.

Mervin

You can certainly make a bitfile with just the FIFO code and load it into the 6I25s FPGA
but unless you integrate the FIFO code into the PCI interface in the FPGA you will have no way to access the card after you load the FIFO code

If you are just planning to test the FIFO code standalone, I would download it to the FPGA via JTAG, and not touch the flash memory

There is a integrated 16 bit FIFO DAQ subsystem in the standard hostmot2 firmware suite complete with PCI/PCIE host interface (adaqfifo=daqfifo16.vhd)

Thank you for your reply PCW.

Now that I have a bitfile, and know how to load it into the card with:
sudo mesaflash --device 5i25 --write toppcihostmot2.bit (for example)
sudo mesaflash --device 5i25 --reload

(What is --readhmid used for ? I saw it several times in the forum)
And mainly how can I test if the code went really inside the card ?
=> Can we use a test file with a LED that would be on if the code reached the card? How do we make it? Or easier, can we change inputs values and see the changes on the outputs ?

Thanks in advance.

Certia

(PS: I also found the .vhd fifo file, if I want to pass words of 32 bits (depth) and 1 bit (width) should I just add depth and width at first then change in "port": "daqdata: in std_logic_vector (15 downto 0)" to "in std_logic"?
At the end, the idea is to make an ARINC 429 which drives 2 outputs.) But let's find out the first problem..