DC analog drives with 7i95T + 7i83
30 Nov 2023 21:42 - 30 Nov 2023 21:47 #286908
by cofford
DC analog drives with 7i95T + 7i83 was created by cofford
Hello all,
I'm retrofitting a Tree 325 with SD1525 DC servos (+/-10v) using a 7i95T with a 7i83 for the analog outputs. I made basic (but very incorrect) ini and hal files, and I can see the 7i83 ports in HalShow. With the cards communicating properly, it's time to focus on ini and hal files for the analog drives.
Am I correct in assuming that I need to set num_pwmgens=0 and num_stepgens=0?
Next. is this the correct way to set up XYZ axes on the 7i83 with encoders on the 7i95? Not looking to discuss values, just basic setup.
ini:
#********************
# Axis X
#********************
[AXIS_0]
TYPE = LINEAR
HOME = 0.0
FERROR = 0.5
MIN_FERROR = 0.05
MAX_VELOCITY = 1.0
MAX_ACCELERATION = 30.0
P = 50.0
I = 0.0
D = 0.0
FF0 = 0.0
FF1 = 1.0
FF2 = 0.0
BIAS = 0.0
DEADBAND = 0.0
MAX_OUTPUT = 0.0
ENCODER_SCALE = 4000.0
OUTPUT_SCALE = 10.0
OUTPUT_MIN_LIMIT = -10.0
OUTPUT_MAX_LIMIT = 10.0
MIN_LIMIT = -13.5
MAX_LIMIT = 13.5
HOME_OFFSET = 0.0
hal:
#*******************
# AXIS X
#*******************
setp pid.x.Pgain [AXIS_0]P
setp pid.x.Igain [AXIS_0]I
setp pid.x.Dgain [AXIS_0]D
setp pid.x.bias [AXIS_0]BIAS
setp pid.x.FF0 [AXIS_0]FF0
setp pid.x.FF1 [AXIS_0]FF1
setp pid.x.FF2 [AXIS_0]FF2
setp pid.x.deadband [AXIS_0]DEADBAND
setp pid.x.maxoutput [AXIS_0]MAX_OUTPUT
setp pid.x.error-previous-target true
net x-index-enable <=> pid.x.index-enable
net x-enable => pid.x.enable
net x-pos-cmd => pid.x.command
net x-vel-cmd => pid.x.command-deriv
net x-pos-fb => pid.x.feedback
net x-output => pid.x.output
# ---PWM Generator signals/setup---
setp hm2_7i95.0.7i83.0.1.analogout0-scalemax [AXIS_0]OUTPUT_SCALE
setp hm2_7i95.0.7i83.0.1.analogout0-minlim [AXIS_0]OUTPUT_MIN_LIMIT
setp hm2_7i95.0.7i83.0.1.analogout0-maxlim [AXIS_0]OUTPUT_MAX_LIMIT
net x-output => hm2_7i95.0.7i83.0.1.analogout0
net x-pos-cmd axis.0.motor-pos-cmd
net x-enable axis.0.amp-enable-out
# enable _all_ sserial pwmgens
net x-enable hm2_7i95.0.7i83.0.1.analogena
# ---Encoder feedback signals/setup---
setp hm2_7i95.0.encoder.00.counter-mode 0
setp hm2_7i95.0.encoder.00.filter 1
setp hm2_7i95.0.encoder.00.index-invert 0
setp hm2_7i95.0.encoder.00.index-mask 0
setp hm2_7i95.0.encoder.00.index-mask-invert 0
setp hm2_7i95.0.encoder.00.scale [AXIS_0]ENCODER_SCALE
net x-pos-fb <= hm2_7i95.0.encoder.00.position
net x-vel-fb <= hm2_7i95.0.encoder.00.velocity
net x-pos-fb => axis.0.motor-pos-fb
net x-index-enable axis.0.index-enable <=> hm2_7i95.0.encoder.00.index-enable
net x-pos-rawcounts <= hm2_7i95.0.encoder.00.rawcounts
# ---setup home / limit switch signals---
net x-home-sw => axis.0.home-sw-in
net x-neg-limit => axis.0.neg-lim-sw-in
net x-pos-limit => axis.0.pos-lim-sw-in
Just want to make sure I'm on the right track here.
Thanks!
I'm retrofitting a Tree 325 with SD1525 DC servos (+/-10v) using a 7i95T with a 7i83 for the analog outputs. I made basic (but very incorrect) ini and hal files, and I can see the 7i83 ports in HalShow. With the cards communicating properly, it's time to focus on ini and hal files for the analog drives.
Am I correct in assuming that I need to set num_pwmgens=0 and num_stepgens=0?
Next. is this the correct way to set up XYZ axes on the 7i83 with encoders on the 7i95? Not looking to discuss values, just basic setup.
ini:
#********************
# Axis X
#********************
[AXIS_0]
TYPE = LINEAR
HOME = 0.0
FERROR = 0.5
MIN_FERROR = 0.05
MAX_VELOCITY = 1.0
MAX_ACCELERATION = 30.0
P = 50.0
I = 0.0
D = 0.0
FF0 = 0.0
FF1 = 1.0
FF2 = 0.0
BIAS = 0.0
DEADBAND = 0.0
MAX_OUTPUT = 0.0
ENCODER_SCALE = 4000.0
OUTPUT_SCALE = 10.0
OUTPUT_MIN_LIMIT = -10.0
OUTPUT_MAX_LIMIT = 10.0
MIN_LIMIT = -13.5
MAX_LIMIT = 13.5
HOME_OFFSET = 0.0
hal:
#*******************
# AXIS X
#*******************
setp pid.x.Pgain [AXIS_0]P
setp pid.x.Igain [AXIS_0]I
setp pid.x.Dgain [AXIS_0]D
setp pid.x.bias [AXIS_0]BIAS
setp pid.x.FF0 [AXIS_0]FF0
setp pid.x.FF1 [AXIS_0]FF1
setp pid.x.FF2 [AXIS_0]FF2
setp pid.x.deadband [AXIS_0]DEADBAND
setp pid.x.maxoutput [AXIS_0]MAX_OUTPUT
setp pid.x.error-previous-target true
net x-index-enable <=> pid.x.index-enable
net x-enable => pid.x.enable
net x-pos-cmd => pid.x.command
net x-vel-cmd => pid.x.command-deriv
net x-pos-fb => pid.x.feedback
net x-output => pid.x.output
# ---PWM Generator signals/setup---
setp hm2_7i95.0.7i83.0.1.analogout0-scalemax [AXIS_0]OUTPUT_SCALE
setp hm2_7i95.0.7i83.0.1.analogout0-minlim [AXIS_0]OUTPUT_MIN_LIMIT
setp hm2_7i95.0.7i83.0.1.analogout0-maxlim [AXIS_0]OUTPUT_MAX_LIMIT
net x-output => hm2_7i95.0.7i83.0.1.analogout0
net x-pos-cmd axis.0.motor-pos-cmd
net x-enable axis.0.amp-enable-out
# enable _all_ sserial pwmgens
net x-enable hm2_7i95.0.7i83.0.1.analogena
# ---Encoder feedback signals/setup---
setp hm2_7i95.0.encoder.00.counter-mode 0
setp hm2_7i95.0.encoder.00.filter 1
setp hm2_7i95.0.encoder.00.index-invert 0
setp hm2_7i95.0.encoder.00.index-mask 0
setp hm2_7i95.0.encoder.00.index-mask-invert 0
setp hm2_7i95.0.encoder.00.scale [AXIS_0]ENCODER_SCALE
net x-pos-fb <= hm2_7i95.0.encoder.00.position
net x-vel-fb <= hm2_7i95.0.encoder.00.velocity
net x-pos-fb => axis.0.motor-pos-fb
net x-index-enable axis.0.index-enable <=> hm2_7i95.0.encoder.00.index-enable
net x-pos-rawcounts <= hm2_7i95.0.encoder.00.rawcounts
# ---setup home / limit switch signals---
net x-home-sw => axis.0.home-sw-in
net x-neg-limit => axis.0.neg-lim-sw-in
net x-pos-limit => axis.0.pos-lim-sw-in
Just want to make sure I'm on the right track here.
Thanks!
Last edit: 30 Nov 2023 21:47 by cofford. Reason: Fixed formatting
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30 Nov 2023 22:21 - 30 Nov 2023 23:01 #286911
by PCW
Replied by PCW on topic DC analog drives with 7i95T + 7i83
That looks close. A 7I77 analog section configuration can
used as a model for a 7I83 configuration with one exception:
The 7I83 has slightly different (separate) enables than the 7I77:
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena0
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena1
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena2
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena3
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena4
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena5
used as a model for a 7I83 configuration with one exception:
The 7I83 has slightly different (separate) enables than the 7I77:
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena0
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena1
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena2
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena3
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena4
33 bit IN FALSE hm2_7i95t.0.7i83.0.1.analogena5
Last edit: 30 Nov 2023 23:01 by PCW.
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30 Nov 2023 22:28 #286912
by tommylight
Replied by tommylight on topic DC analog drives with 7i95T + 7i83
This is for wiring and testing and tuning with analog servos and Mesa 5i25/7i77, everything here applies to your case, only the encoder stuff goes to 7i95T and analog stuff to 7i83.
You should read through at least once before starting, it has detailed wiring and testing stuff one by one, not "wire everything and let the smoke out".
Regarding tuning, se the bottom of it and if you have the required info it will save you quite some time.
You should read through at least once before starting, it has detailed wiring and testing stuff one by one, not "wire everything and let the smoke out".
Regarding tuning, se the bottom of it and if you have the required info it will save you quite some time.
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30 Nov 2023 22:48 - 30 Nov 2023 23:14 #286913
by cofford
Is there supposed to be a file or link attached?
Replied by cofford on topic DC analog drives with 7i95T + 7i83
This is for wiring and testing and tuning with analog servos and Mesa 5i25/7i77, everything here applies to your case, only the encoder stuff goes to 7i95T and analog stuff to 7i83.
You should read through at least once before starting, it has detailed wiring and testing stuff one by one, not "wire everything and let the smoke out".
Regarding tuning, se the bottom of it and if you have the required info it will save you quite some time.
Is there supposed to be a file or link attached?
Last edit: 30 Nov 2023 23:14 by cofford.
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30 Nov 2023 23:24 #286916
by tommylight
Replied by tommylight on topic DC analog drives with 7i95T + 7i83
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05 May 2024 16:46 - 05 May 2024 17:35 #299826
by NT4Boy
Replied by NT4Boy on topic DC analog drives with 7i95T + 7i83
When I do halcmd grep 7i83 with my 7i95t and connected 7i83 get.
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena0
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena1
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena2
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena3
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena4
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena5
which is not quite the same.
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena0
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena1
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena2
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena3
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena4
30 bit IN FALSE hm2_7i95.0.7i83.0.1.analogena5
which is not quite the same.
Last edit: 05 May 2024 17:35 by NT4Boy. Reason: Typo
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05 May 2024 16:51 #299827
by PCW
Replied by PCW on topic DC analog drives with 7i95T + 7i83
Yes, the 7I83 is a bit different than the analog section of the 7I77
since is has individual analog enables rather than the 7I77s single
enable for analog outputs 0..4 and one for analog output 5.
since is has individual analog enables rather than the 7I77s single
enable for analog outputs 0..4 and one for analog output 5.
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05 May 2024 17:37 #299830
by NT4Boy
Replied by NT4Boy on topic DC analog drives with 7i95T + 7i83
Sorry, I made a typo. I meant' 7i95t (which I have edited above).
I was concerned that the halcmd show data says 7i95, not 7i95t.
I was concerned that the halcmd show data says 7i95, not 7i95t.
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05 May 2024 17:50 #299832
by PCW
Replied by PCW on topic DC analog drives with 7i95T + 7i83
The 7I95T shows up as a 7I95 in hal (since its compatible in every way)
(the 7I92T is similar)
(the 7I92T is similar)
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