Analog servos: torque mode, velocity mode, both?

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29 Mar 2014 16:02 #45363 by DaBit
OK, that is what I expected, but not what I hoped :laugh:
It does make having a small error between the comamnd and feedback less important though, as long as it is not excessive enough to trip a following error

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01 Apr 2014 23:20 #45484 by DaBit
I just ordered a 6i25+7i77, and I will sell the 5i25+7i76 set.

Now, what about firmware? No standard bitfile gives me exactly what I want. 7i77+7i76 comes close if I do the PDM bitstream for the spindle in software. 7i77+PROB_RFX would be even slightly better but isn't a standard configuration.

The most ideal configuration would be 7i77 on one port and the other port equipped with:
- 2x stepgen (4 pins)
- 4x muxed encoder (7 pins).
- 3x PWM/PDM generator (3 pins).
- 3x GPIO

My VHDL is a little rusty and it has been a long time since I saw an FPGA from the inside, but when scanning through the VHDL it seems that creating another PIN_xxx file and using that in TopPCIHostMot2.vhd covers most of what is required to build a custom bitfile? Is there more documentation available somewhere?

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02 Apr 2014 01:07 #45485 by PCW
Tom Light has a nice tutorial:

tom-itx.dyndns.org:81/~webpage/emc/xilin...14_install_index.php

Basically the build process is defined by the top level file and the PIN_XXX.vhd file
so for a custom configuration you take a existing PIN_XXX,vhd file and
change the pin descriptor and module sections to match your requirements,
include the new PIN_XXX.vhd file in the top level source and compile.

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02 Apr 2014 04:48 #45489 by DaBit
Thanks! I'll see how far I get.

Looks like I have some serious downloading to do first...

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03 Apr 2014 04:46 #45514 by DaBit
So I downloaded ISE 14.7, installed it as WebPack, and built a standard 2x7i77 configuration. I am getting a lot of warnings I am not really comfortable with such as 'BAR0Reg[15] has no driver' and 'The signal <ahostmot2/makesserialmod.makesserials[0].asserial/interfaceramout0/Mram_RAM5_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the design', but oh well.

Next I loaded the resulting bitfile onto a 5i25 without any daughterboards connected (waiting for my 7i77 to arrive). I am seeing pins for 12 encoders. Now, that was easy; I expected a bit more sweat.

Questions:
1) Is there a method to force reconfiguration of the FPGA without a (cold) reboot? Laptop with ISE is inside the house, milling PC is in the shed. Would make a bit of tinkering much easier.
I could use a xilinx download cable, but then I still need to trigger a PCI bus enumeration I suppose...

2) When looking at this:
package PIN_7I77_7I76_34 is
	constant ModuleID : ModuleIDType :=( 
		(WatchDogTag,	x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,		WatchDogNumRegs,		x"00",	WatchDogMPBitMask),
		(IOPortTag,		x"00",	ClockLowTag,	x"02",	PortAddr&PadT,					IOPortNumRegs,			x"00",	IOPortMPBitMask),
		(MuxedQcountTag,		MQCRev,	ClockLowTag,	x"08",	MuxedQcounterAddr&PadT,		MuxedQCounterNumRegs,x"00",	MuxedQCounterMPBitMask),
		(MuxedQCountSelTag,	x"00",	ClockLowTag,	x"01",	NullAddr&PadT,					x"00",					x"00",	x"00000000"),
		(SSerialTag,	x"00",	ClockLowTag,	x"01",	SSerialCommandAddr&PadT,	SSerialNumRegs,		x"10",	SSerialMPBitMask),
		(StepGenTag,	x"02",	ClockLowTag,	x"05",	StepGenRateAddr&PadT,		StepGenNumRegs,		x"00",	StepGenMPBitMask),
		(LEDTag,			x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,					LEDNumRegs,				x"00",	LEDMPBitMask),
..
..
constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	 sec pin								-- 	P3 	DB25
		IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, 				-- I/O 00	PIN 1
		IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, 				-- I/O 01	PIN 14
		IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, 				-- I/O 02	PIN 2
		IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, 				-- I/O 03	PIN 15
		IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, 				-- I/O 04	PIN 3
		IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, 				-- I/O 05	PIN 16
		IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, 				-- I/O 06	PIN 4
..
..

There is something I do not understand. '.. (SSerialTag, x"00", ClockLowTag, x"01" ....' defines a SSerial module, version 00, clocked by ClockLow, 1 instance, right?
But then in the pin descriptions I see three SSerial modules being connected to the IO pins?

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03 Apr 2014 04:58 #45515 by andypugh

1) Is there a method to force reconfiguration of the FPGA without a (cold) reboot?


My shed-PCs are all set to Wake on LAN.

So via ssh I can sudo shutdown -h now
Then flick the breaker to the workshop
Then WoL the PC in question and log back in.

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03 Apr 2014 05:08 #45516 by DaBit
I remember WoL not working with that Intel Pro1000 card I use, but I can try again. If that works it is a good solution.

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03 Apr 2014 05:29 #45521 by PCW

There is something I do not understand. '.. (SSerialTag, x"00", ClockLowTag, x"01" ....' defines a SSerial module, version 00, clocked by ClockLow, 1 instance, right?
But then in the pin descriptions I see three SSerial modules being connected to the IO pins?


The sserial host interface has up to 8 channels per instance for space efficiency
(since each instance has RAM, ROM, a timer, a CRC generator/checker and a processor)
so you have one sserial module with 3 channels
(you can have up to a maximum of 4 modules so 32 channels max)


The warnings are harmless, mainly the result of using generic packages that have some logic
that gets trimmed away I periodically do cleanups but only when there are 200 or more warnings

There are some warnings you cannot eliminate...

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15 Apr 2014 17:23 - 15 Apr 2014 18:56 #45964 by DaBit
What is preferred on this forum? Start a new topic for different questions, or continue in an existing topic?

[edit]
Moved the question to a new topic here .
[/edit]
Last edit: 15 Apr 2014 18:56 by DaBit. Reason: Split off an unrelated question to a new topic

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15 Apr 2014 18:41 #45969 by BigJohnT
Searching is much easier if you start a new topic for a new question.

JT

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