Hi, i've been looking into adding better arisc implementation of arisc_stepgen and arisc_gpio, esp for orange pi.
I have _just_ rediscovered the relevant code in the original John Kasunich (JMK) stepgen code, It's in 'timer1 timer2 timer3'.
The correct rules for step timing are in the man page for stepgen. Most relevant are the definitions of dirsetup and dirhold, and how they can be implemented in code. I made some assumptions that they must begin with falling edge of step signal. Then i found them to be just as sketched on paper.
The relevant bits are in the code for three timers. The technique used avoids a lot of math by assuming the entire time (steplength, dirsetup, dirhold and combinations of those) can be represenedt by part of a 32 bit value. Each timer is a 32 bit accumulator. An increment is calculated for each timer. Every cycle adds one increment to the accumulator. A single high water bit mark is chosen in the accumulator. The high water bit becomes SET when the sum of increments pass it ( whne the time has elapsed). This methiod is easy on the cpu load.
This method is clever but convoluted. It is called a DDS in the code (Direct Digital Synthesis) but dont bother trying to allign the code with the Wikipedia (or other) defintion. The high water mark and sized increment describes it better.
Anyway, discovery of the code and technique is important to enabling similar in the arisc_stegen code.
Understanding the size of the base and servo periods is very important. The worst timin scenario is taking a new step in a different direct than last. You have to hold the step line of steplen nS, and you have to hold the direction line for dirhold nS, and you have to set the new directionline and wait dirsetup time before taking the new step.
If you have a steplen of 5000nx and a dirhold of 20000ns and a dirsetup of 20000, then you can calculate the worse case time with safeperiod = jitter + steplen + dirhold + dirsetup. with RPi or OPi jitter of 50000nS, the safeperiod is 50+5+20+20 = 95uS. not very fast
.
that's 10526 steps/sec ( dblstep) or 79mm/sec for my .0075 stepsize
or 39.5mm/sec w/o dblstep (2.3meters/min, ok but pretty slow)
This make the arisc driver appealing because it removes the jitter component of formula.
In arisc ( without jitter), the step rate increases
1sec/45uS=22222step/sec.(with dblstep)
thats 10meters/min at my stepsize of .0075
and 5meter/min without doublstep
I need to use the arisc_gpio code in a loop to see if the arisc (like a co_processor ) is verifiable and suited to realtime ( is really deterministic ).
Also, this means that the arisc 'core' doesnt need to be re-wrtten, only th arisc_stepgen and possibly the arisc_gpio code.
I do need to learn howto build it ( it uses the arisc instruction set),
and learn if it needs any installation in the arisc space.
Bye for now, lots todo.
Hope this is hopeful
tjtr33
