ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

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07 Feb 2022 17:53 #234264 by tuxcnc
I tried on official Linuxcnc Debian Buster distro (gcc 8.3.0).
The same problem.

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07 Feb 2022 18:16 #234267 by ALittleOffTheRails
Read the halcompile section in the docs, it would seem it can’t compile userpace C files.
It would seem that you need to put the c & h files in the source tree and do a full build.
That how I interpret it.

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07 Feb 2022 18:50 #234271 by tuxcnc

Read the halcompile section in the docs, it would seem it can’t compile userpace C files.
It would seem that you need to put the c & h files in the source tree and do a full build.
That how I interpret it.
 

Thanks.
halcompile --compile colorcnc.c  and halcompile --install colorcnc.c works and Linuxcnc starts.
I can't check more, because I'm waiting for cards.

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13 Feb 2022 17:50 #234714 by cncwhacko
Thanks for posting this! I just picked up a 5A-75E v8.0 board to give this a try as it sounds like a fun project. I've tried flashing the built variant but seems to default to 7.1 spec in pinout which doesn't align with my version (V8.0). The built file flashes successfully but no PHY connectivity (on either port).

Upon further inspection, It seems the pinout is similar to previous V6 documentation of this board, with PHY reverting back to REALTEK RTL8211FD. Anyone have any guidance on how to confirm if all pinouts are the same on V8.0 as it is with V6? If so i think would need to modify colorlight_5a_75e.py as it refers to the 7.1 spec and errors as such:
ERROR: Cell 'gpio_in24$tr_io' cannot be bound to bel 'X72/Y5/PIOD' since it is already bound to cell 'gpio_in28$tr_io' 0 warnings, 1 error Traceback (most recent call last):   File "./colorlight_5a_75e.py", line 685, in     main()

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14 Feb 2022 03:14 #234783 by ALittleOffTheRails
Doesn't appear to be much info. Maybe a boundary scan ?

Does Litex support the v8.0 ?

I'm playing around with a 5A-75B v7.1 and am just starting to work out which signal goes to which '245 so I know which ones to replace with '245LVC so I can get some inputs.

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14 Feb 2022 18:47 #234848 by cncwhacko
Was able to get the V6 pinout variant to build when i commented out J16 gpio inputs in the file. I then flashed that resulting file and now have phy1 responding to pings on the configured ip address!

I will look a bit into the pin_scan script in github.com/q3k/chubby75/tree/master/5a-75b/pin-scan to see if I can get it to work with the v8, but at surface level, v6 mapping seems to work with V8 board, however, only have validated the phy and jtag stuff to be the same.

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17 Feb 2022 09:34 #235109 by TOLP2
Very nice development. I just ordered mine board of AliExpress for 20 Euros. Contributing to the Python code / firmware and the driver for LinuxCNC is no problem for me. However: can somebody recommend a JTAG programmer for this card?

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17 Feb 2022 14:43 #235137 by cncwhacko
Any openocd supported device should work OK. I just picked up a ft232h based one.

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18 Feb 2022 01:31 #235204 by ALittleOffTheRails
I use an USB-Blaster clone and openFPGALoader.

What would be great is:

To have the FPGA configured for all pins as outputs & a Linuxcnc comp to suit. This would aid in figuring out what pin goes to which buffer on the 5A-75E V7.1
Then I could clobber up a pyvcp panel, simialr to the Parallel Port tester to control the pins.

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18 Feb 2022 18:27 #235259 by cncwhacko
For your board are you seeing much difference from what was documented in github.com/q3k/chubby75/blob/master/5a-75e/hardware_V7.1.md ?

It has the mapping of HUB75 pin to J[XX] connectors on the board already.


On my board (5A-75E V8.0) i just loaded the pin_scan program which emits UART signal on every single port so you can go around with serial cable onto each FPGA pin and it will tell you the pin that is mapped. All of my v8 pins I've scanned have aligned with the 5A-75E V6 of the board documented but i haven't completed 100% yet. Of the 10 or so i tested, they were all the same.

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