New project, litehm2: a hostmot2 port to linsn rv901t

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29 May 2023 18:14 #272447 by sensille

Not 16 ?
I read that there are 10 outputs on J600 or J601 and 6 on the JP4, two buffered and four unbuffered.

In theory you could use those 4 unbuffered lines as output, too. But that would mean you have to deal with FPGA levels directly, without the convenience (and protection) of a driver. Also I use 2 of them for UART-debugging during development.

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30 May 2023 03:01 #272478 by tuxcnc

it still needs one more patch for litex-boards.
 

 
Try this

File Attachment:

File Name: linsn_rv901t.patch
File Size:1 KB


Compilation still doesn't work for me.
Still <TypeError: get_mem_data() got an unexpected keyword argument 'data_width'> and after removing  line containing "data with" :
root@HP-15s:~/litehm2-master#./litehm2.py
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/root/litehm2-master/./litehm2.py", line 170, in <module>
    main()
  File "/root/litehm2-master/./litehm2.py", line 163, in main
    soc = LiteHM2(ip_address=args.ip_address,
  File "/root/litehm2-master/./litehm2.py", line 78, in __init__
    main_ram_init = get_mem_data(builddir + "/firmware/firmware.bin",
  File "/opt/litex/litex/litex/soc/integration/common.py", line 44, in get_mem_data
    regions = get_mem_regions(filename_or_regions, offset)
  File "/opt/litex/litex/litex/soc/integration/common.py", line 28, in get_mem_regions
    raise OSError(f"Unable to find {filename} memory content file.")
OSError: Unable to find build/firmware/firmware.bin memory content file.
Attachments:

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30 May 2023 03:55 #272479 by tuxcnc

In theory you could use those 4 unbuffered lines as output, too.
 

I loaded rv901t_stock__example_in.bit into flash memory, I get answers to ping.
I will do more tests later.

Could you compile configuration with all pins available on JP4 and without a serial port?
16 outputs is more than at the LPT port, I think that for many people are enough ...

If this works, you will be able to do 4 Stepgen, 2 PWM and 6 outputs.
This is enough for a milling machine with a fourth axis.

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30 May 2023 04:42 #272480 by tuxcnc
4th axis explanation :
File Attachment:

imgbox.com/JN9HeNH2

Depending on the state of the Toggle signal, at the multiplexer's output you will get either stepgen signals (normal axis), or the PWM signal as a steppe (axis as a spindle).
PWM as STEP.
By switching from the axis to the spindle you will lose position, but this is how it works.
Multiplexer works as buffer too.

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30 May 2023 04:59 #272481 by sensille
you have to build with make

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30 May 2023 05:22 #272482 by sensille

In theory you could use those 4 unbuffered lines as output, too.
 
I loaded rv901t_stock__example_in.bit into flash memory, I get answers to ping.
I will do more tests later.

Could you compile configuration with all pins available on JP4 and without a serial port?
16 outputs is more than at the LPT port, I think that for many people are enough ...

If this works, you will be able to do 4 Stepgen, 2 PWM and 6 outputs.
This is enough for a milling machine with a fourth axis.


 

I can, later this day. I have to think about the implications of not having the serial.
But instead of adding a multiplexer, isn't it easier to do the board modification the way IlyaKw described?

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30 May 2023 11:49 #272494 by sensille

In case of RV901T you should cut one trace in two places then solder it to GND and add a smd 0805 1k resistor to 3V3. In the end you will get U603, U607, U602, U606 as input and U605, U601, U604, U600 as output ports.


Do you by any chance have more information on where to cut it? A pic, or a link?

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30 May 2023 14:22 #272498 by tuxcnc

But instead of adding a multiplexer, isn't it easier

Must be multiplexer.
Hardware or software, but multiplexer.
You can't replace multiplexer by add outputs.
The idea of 4th axis is switching the STEP/DIR inputs of stepper (servo) motor controller.
In mode "axis" you can drive motor by g-codes, in mode "spindle" 4th axis turns independent of g-code (as in lathe).
You may use external generator for "spindle" velocity, but you may not drive it from LinuxCNC.
Use of PWM output give this ability.
In other words, in this case, the PWM is in fact frequency generator, it is a trick, but should works.

The <IndexError: list index out of range> is from litehm2.py and use of make command nothing to do with it. (Of course you are right, compilation should be run by make command).

BTW.
I think, most of LinuxCNC users want drive three axis milling machine, or two axis lathe, so the signals for that should be at J600 or J601 connector.
Some users want four axis machine, so 4th's STEP/DIR signals may be at JP4 connector, but should be buffered.
The PWM signals are for advanced users, so these may be unbuffered at JP4 connector.
The multipurpose outputs should be at J600 or J601 connector.
This is to avoid situation when beginers must use unbuffered signals at JP4.

 

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30 May 2023 15:43 #272503 by sensille

The <IndexError: list index out of range> is from litehm2.py and use of make command nothing to do with it. (Of course you are right, compilation should be run by make command).


litehm2.py expects an initial firmware.bin and loader.bin to be present. The makefile generates a dummy before calling litehm2.py. Not the best solution, but the least intrusive I could think of at that time.
If it still fails when called from make (and without any lines removed), can you please give me some more output again?

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30 May 2023 17:24 #272508 by tuxcnc

can you please give me some more output again?

Of course, however it is the same.
root@HP-15s:~/litehm2-master# cd configs
root@HP-15s:~/litehm2-master/configs# ln -s rv901t_stock__example_in.conf rv901t.conf
root@HP-15s:~/litehm2-master/configs# cd ..
root@HP-15s:~/litehm2-master# make
make -f Makefile.target TARGET=rv901t
make[1]: Wejście do katalogu '/root/litehm2-master'
dd if=/dev/zero of=build/rv901t/firmware/firmware.bin bs=32k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 32768 bajtów (33 kB, 32 KiB), 0,000469345 s, 69,8 MB/s
dd if=/dev/zero of=build/rv901t/firmware/loader.bin bs=4k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 4096 bajtów (4,1 kB, 4,0 KiB), 0,000244094 s, 16,8 MB/s
./litehm2.py --builddir=build/rv901t --config=configs/rv901t.conf
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-05-30 19:18:00)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
Traceback (most recent call last):
  File "/root/litehm2-master/./litehm2.py", line 170, in <module>
    main()
  File "/root/litehm2-master/./litehm2.py", line 163, in main
    soc = LiteHM2(ip_address=args.ip_address,
  File "/root/litehm2-master/./litehm2.py", line 119, in __init__
    self.add_ethernet(
  File "/opt/litex/litex/litex/soc/integration/soc.py", line 1538, in add_ethernet
    ethmac = LiteEthMAC(
  File "/opt/litex/liteeth/liteeth/mac/__init__.py", line 52, in __init__
    wishbone_interface = LiteEthMACWishboneInterface(
  File "/opt/litex/liteeth/liteeth/mac/wishbone.py", line 45, in __init__
    mem_or_size = self.sram.reader.mems[n],
IndexError: list index out of range
make[1]: *** [Makefile.target:10: litehm2] Błąd 1
make[1]: Opuszczenie katalogu '/root/litehm2-master'
make: *** [Makefile:8: bitstreams/rv901t.bit] Błąd 2

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