New project, litehm2: a hostmot2 port to linsn rv901t

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30 May 2023 17:51 - 30 May 2023 17:56 #272510 by sensille
Damn. I have a fix for that in my local repo which i seem to have forgotten to submit:

`
diff --git a/liteeth/mac/wishbone.py b/liteeth/mac/wishbone.py
index 9a76dfc..f32b346 100644
--- a/liteeth/mac/wishbone.py
+++ b/liteeth/mac/wishbone.py
@@ -40,7 +40,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
 
         # Wishbone SRAM interfaces for the reader SRAM (i.e. Ethernet TX).
         wb_tx_sram_ifs =
-        for n in range(nrxslots):
+        for n in range(ntxslots):
             wb_tx_sram_ifs.append(wishbone.SRAM(
                 mem_or_size = self.sram.reader.mems[n],
                 read_only   = False,
`

EDIT: scratch that, it was part of github.com/enjoy-digital/liteeth/pull/124. You should probably update the rest of litex, too.
Last edit: 30 May 2023 17:56 by sensille.

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30 May 2023 18:29 #272512 by tuxcnc

You should probably update the rest of litex, too.
 

I installed litex a few days ago.
Patched and this error gone, but now <ERROR:SoCBusHandler:Not enough Address Space to allocate Region.>
root@HP-15s:~/litehm2-master# make
make -f Makefile.target TARGET=rv901t
make[1]: Wejście do katalogu '/root/litehm2-master'
dd if=/dev/zero of=build/rv901t/firmware/firmware.bin bs=32k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 32768 bajtów (33 kB, 32 KiB), 0,000342593 s, 95,6 MB/s
dd if=/dev/zero of=build/rv901t/firmware/loader.bin bs=4k count=1
1+0 przeczytanych rekordów
1+0 zapisanych rekordów
skopiowane 4096 bajtów (4,1 kB, 4,0 KiB), 0,000228353 s, 17,9 MB/s
./litehm2.py --builddir=build/rv901t --config=configs/rv901t.conf
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-05-30 20:22:40)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00001000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCRegion:Region size rounded internally from 0x00005000 to 0x00008000.
INFO:SoCBusHandler:Allocating IO Region of size 0x00005000...
ERROR:SoCBusHandler:Not enough Address Space to allocate Region.
make[1]: *** [Makefile.target:10: litehm2] Błąd 1
make[1]: Opuszczenie katalogu '/root/litehm2-master'
make: *** [Makefile:8: bitstreams/rv901t.bit] Błąd 2

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30 May 2023 18:33 #272513 by sensille
That is another patch that is already in master. Also from the above pull/124 you probably missed the rx-corruption path.
I also installed litex a few days ago (with litex_setup.py) and all the patches are in there.

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30 May 2023 18:43 #272514 by sensille
I tried to build a config according to your specs, but it doesn't meet timing constraints yet, it might be a bit full. Still looking...

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30 May 2023 19:17 #272515 by sensille
I pushed a conf+bitstream to branch jp4 (github.com/sensille/litehm2/tree/jp4), can you please have a look if that suites your needs? I haven't tested it yet.

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30 May 2023 20:08 #272516 by tuxcnc

I also installed litex a few days ago (with litex_setup.py) and all the patches are in there.
 

Compiled.
Well, upgrade is when fixing old bugs and adding new, they say...
First, I run /opt/litex/litex_setup.py --update
After that I got error meaning "there is no spiflash section in  /opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py".
In fact, there is no.
I patched as below, but I don't know the pins for flash are correct.
After that compilation went, very long time (~ 30 min), but went.
The firmware not tested yet.
diff -Naur old/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py new/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py
--- old/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py<->2023-05-30 21:05:02.018074388 +0200
+++ new/opt/litex/litex-boards/litex_boards/platforms/linsn_rv901t.py<->2023-05-30 21:26:10.730300504 +0200
@@ -54,6 +54,16 @@
         IOStandard("LVCMOS33")
     ),
.
+    # SPIFlash (W25Q32JV)
+    ("spiflash", 0,
+        # clk
+        Subsignal("cs_n", Pins("T3")),
+        Subsignal("clk",  Pins("R11")),
+        Subsignal("mosi", Pins("T10")),
+        Subsignal("miso", Pins("P10")),
+        IOStandard("LVCMOS33"),
+    ),
+
     # SDR SDRAM
     ("sdram_clock", 0, Pins("K11"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
     ("sdram_clock", 1, Pins("K12"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
@@ -82,6 +92,19 @@
 # Connectors ---------------------------------------------------------------------------------------
.
 _connectors = [
+    # Near Molex, two rows, ten pins, described as DOT.
+    ("JP4", {
+        # Buffered through U610 chan 0
+        7: "F12",
+        # Buffered through U610 chan 1
+        8: "F6",
+        # Unbuffered !!!
+#        3: "H5",
+        4: "G5",
+#        5: "G6",
+        6: "F5"
+    }),
+
     # Lower connector on board. Pin 1 marked with silkscreen layer, pins then
     # alternating through the two rows of the connector.
     ("J600", {

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30 May 2023 20:15 #272517 by sensille
Yes, see github.com/litex-hub/litex-boards/pull/506. Don't add JP4, i do that in hostmot2.py.

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30 May 2023 20:51 #272518 by IlyaKw

In case of RV901T you should cut one trace in two places then solder it to GND and add a smd 0805 1k resistor to 3V3. In the end you will get U603, U607, U602, U606 as input and U605, U601, U604, U600 as output ports.


Do you by any chance have more information on where to cut it? A pic, or a link?

If you wouldn't mind to post this info here then  tomorrow I will do this with pics and an explanation.
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31 May 2023 18:43 #272597 by IlyaKw
RV901T Modification
There are two options. 
The first one consists of:
1. removing of R608 resistor (upper part of the board)
2. cutting the track which goes to FPGA F13 pin,
3. solder the resistor (0805 1K) that will pull up to 5V upper segment of the track
4. cutting the track  (bottom right corner)
5. connecting its bottom part to GND polygon

The second one consist of:
1. cutting the track (bottom right corner)
2. connecting its bottom part to GND polygon
3. in FPGA "connect" F13 pin to Vcc

All of these options work.

 
 

I hope I was able to explain the point
Regarding the supply voltage of the 245 buffers. Currently I have two boards that works with no modification of supply voltage. It is 5V (4.89 in fact). Of course it does not meet the requirements DC characteristics of Spartan6 but it works.I can't tell how long this will last.
It would be safer to power them from a lower voltage. One easy way to add a  silicon diode to the +5V that supply the board.
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31 May 2023 19:13 #272600 by tommylight
Seems very clear on what to remove, cut, add, and solder.
Thank you.

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