Question about custom BOB for a 7i92

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29 Apr 2023 23:50 - 29 Apr 2023 23:52 #270266 by blazini36

Yes, you could add an external SPI port
Note that if you buffer MISO you need to
enable the buffer with the chip select
(and that buffering will slow things down a bit)
 

I was planning on using an on-board jumper to enable all buffers as well as the buffering the external CS (maybe not necessary with the decoder output), so basically the connector is dead unless the jumper is on and presumably not being instantiated via the component.....or is there some issue with the MISO buffer being on when the external chip is not selected via CS?

Also thinking of multiplexing the outputs so I can squeeze 2 more stepgens in there for rev2. I only see "OutM" in the hostmot2 docs, I assume that's an output mux that I can use a multiplexer with 3 address lines and a direction line with like inMux? Can the FPGA handle 8 stepgens along with the rest of what I stuffed in there?.

That first pinout still relates to the PCB I have on the way so that's the actual firmware I need for now (with the frame pin on CS_A1 as you suggested).
Last edit: 29 Apr 2023 23:52 by blazini36.

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30 Apr 2023 00:31 #270271 by PCW
There is no muxed output module currently So I would not count on that

(If i do this eventually I would use a shift register like the 74HCT595)

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30 Apr 2023 02:03 - 30 Apr 2023 02:22 #270273 by blazini36
Have to figure out whether I want to ditch SS or not then, starting to ask alot of that little board.

I'm not terribly familiar with decoders, multiplexers or SPI in general but this is what I'm looking at.
 

Edit, Edit,
Had to look at it about three times to understand the issue. I suppose the issue is the buffer overcoming the MISO line cancelling out the other devices on the line?

BTW, appreciate the help.....didn't expect it to get this complicated.
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Last edit: 30 Apr 2023 02:22 by blazini36.

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30 Apr 2023 02:48 #270281 by blazini36
Maybe something like this
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01 May 2023 03:31 - 01 May 2023 03:34 #270374 by PCW
Note that you could use a '125 (active low enables)
instead of the '126 to eliminate the inverter

Also you have the input/output swapped on the buffers MISO signal
Last edit: 01 May 2023 03:34 by PCW.

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01 May 2023 03:47 #270375 by blazini36

Note that you could use a '125 (active low enables)
instead of the '126 to eliminate the inverter

Also you have the input/output swapped on the buffers MISO signal
 

Good catch, I just threw that together quick so I could try to understand the issue with the MISO buffer you mentioned and that symbol wasn't in the library.

good call on the '125 chip, I'll have to find some kind of resource for common ICs and their differences, like active low enables.

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01 May 2023 04:07 #270376 by blazini36
Also, I don't know if bspi is using active high or low to enable the decoder. I have the active high in use on that sheet. I'm planning to use the pull down jumper on both headers if that matters.

I'm also using the non-inverted output of the HC251 chip assuming that's what InMux is looking for, is that correct?

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01 May 2023 13:49 #270409 by PCW
I think the frame default is active low
(though can be inverted in the hal file)

On the 251 I would use the inverted output
as the default is also active low

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04 May 2023 17:10 #270648 by blazini36
PCW, any word on that firmware?

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04 May 2023 17:51 #270655 by PCW
Do you have a final pinout?

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