ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

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20 Jul 2022 17:56 - 20 Jul 2022 18:08 #247865 by vit74vit
To check the hardware, I tried Inga's colorcnc project ( this ). Inputs, outputs and PWM work correctly. There are questions with stepgens, but they are related to hal file settings.
Last edit: 20 Jul 2022 18:08 by vit74vit.

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25 Jul 2022 10:05 #248233 by mehdidadash
Is it possible to make 5 axis closed loop cnc with the 5A-75E/5A-75B boards ? 

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25 Jul 2022 15:50 #248267 by xu
Dear svb
To run LiteX-CNC do I have to install LiteX first?
Can a tutorial on detailed commands be issued?

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25 Jul 2022 18:51 #248275 by svb

Dear svb
To run LiteX-CNC do I have to install LiteX first?

Yes, of course

Can a tutorial on detailed commands be issued?

What tutorial you mean?
For LiteX? On github LiteX page.
For Litex-CNC? On github Litex-CNC page.
The following user(s) said Thank You: xu

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25 Jul 2022 18:55 #248276 by svb

Is it possible to make 5 axis closed loop cnc with the 5A-75E/5A-75B boards ? 
 

It will be available in the future if there are opportunities and time for TOLP2 to make this functionality :)

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25 Jul 2022 22:13 #248283 by kwarup
Hi, I'm having troubles to create the firmware, can you help ?

INFO:SoC:
INFO:SoC:Initial SoC:
INFO:SoC:
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU None added.
INFO:SoC:CPU None adding IO Region 0 at 0x00000000 (Size: 0x100000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:ECP5PLL:Creating ClkOut0 sys of 50.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 sys_ps of 50.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/usr/lib/python3.7/runpy.py", line 193, in _run_module_as_main
    "__main__", mod_spec)
  File "/usr/lib/python3.7/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/durval/dev/LiteX-CNC/firmware/__main__.py", line 36, in <module>
    build_soc()
  File "/home/durval/.local/lib/python3.7/site-packages/click/core.py", line 1130, in __call__
    return self.main(*args, **kwargs)
  File "/home/durval/.local/lib/python3.7/site-packages/click/core.py", line 1055, in main
    rv = self.invoke(ctx)
  File "/home/durval/.local/lib/python3.7/site-packages/click/core.py", line 1404, in invoke
    return ctx.invoke(self.callback, **ctx.params)
  File "/home/durval/.local/lib/python3.7/site-packages/click/core.py", line 760, in invoke
    return __callback(*args, **kwargs)
  File "/home/durval/dev/LiteX-CNC/firmware/__main__.py", line 24, in build_soc
    soc = firmware_config.generate(fingerprint)
  File "/home/durval/dev/LiteX-CNC/firmware/soc.py", line 263, in generate
    soc=self)
  File "/home/durval/dev/LiteX-CNC/firmware/soc.py", line 126, in __init__
    ip_address=str(etherbone.ip_address))
  File "/home/durval/dev/litex/litex/soc/integration/soc.py", line 1694, in add_etherbone
    etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=etherbone_cd)
  File "/home/durval/dev/liteeth/liteeth/frontend/etherbone.py", line 490, in __init__
    self.submodules.record = record = LiteEthEtherboneRecord(buffer_depth=buffer_depth)
  File "/home/durval/dev/liteeth/liteeth/frontend/etherbone.py", line 323, in __init__
    self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver(buffer_depth)
  File "/home/durval/dev/liteeth/liteeth/frontend/etherbone.py", line 191, in __init__
    assert buffer_depth <= 256
AssertionError
durval@debcnc:~/dev/LiteX-CNC$ python3 -m firmware examples/5a-75e-hello-gpio.json 

 

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26 Jul 2022 03:12 #248294 by vit74vit
File "/home/durval/dev/liteeth/liteeth/frontend/etherbone.py", line 191, in __init__
assert buffer_depth <= 256
Edit buffer_depth in this file., change value 256->2000

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26 Jul 2022 07:16 #248298 by svb
Hi.
Small instruction

Pre-requisite.
Check for LiteX environment installed. (Read LiteX wiki how to install LiteX)
Check for OSS-CAD-SUITE installed

1. Clone LiteX-CNC GIT repo, branch envoders!!!
git clone github.com/Peter-van-Tol/LiteX-CNC.git -b envoders LiteX-CNC
2. cd LiteX-CNC
3. python3 -m firmware examples/Your_json_Examples.json
If all installed correct you do not have any errors and get your test config ok.
4. For example, you select examples/5a-75e.json
In LiteX-CNC after running command from "3." you now have forder named as you examples, i.e. 5a-75e.
cd 5a-75e
you will see 2 folders - software and gateware. We need cd to gateware
in this folder run Shell script,for my examples will be build_colorlight_5a_75e.sh
sh ./build_colorlight_5a_75e.sh
if all pre-req installed correctly after this script is finished you get build_colorlight_5a_75e.bit and build_colorlight_5a_75e.svf file in this folder
Flash any of this file with your preffered soft.
End




 
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26 Jul 2022 07:17 #248299 by svb

File "/home/durval/dev/liteeth/liteeth/frontend/etherbone.py", line 191, in __init__
assert buffer_depth <= 256
Edit buffer_depth in this file., change value 256->2000

 


No No No No!!!!

buffer_depth MUST BE LESS or equal 256!!!
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26 Jul 2022 08:02 - 26 Jul 2022 08:04 #248301 by vit74vit
In old version Litex-CNC:
buffer_depth: int = Field(
1060,
help_text="The size of the buffer for the Etherbone protocol. Should be "
"large enough to fit all data for communication with LinuxCNC. TODO: check "
"whether this size can be automatically determined."
)

To kwarup:
probably you use the main branch, use branches envoders
Last edit: 26 Jul 2022 08:04 by vit74vit.

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